diff options
author | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2014-10-16 05:49:41 -0400 |
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committer | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2014-10-16 05:49:41 -0400 |
commit | e0074324bacf500f9d0cc11ebc6e2f29bf3d8ba1 (patch) | |
tree | 0ecfcd3d7e3633251a8f632fe7ee5542a67fb8df /src/cpu/simple/timing.cc | |
parent | 9d35d48e848914fd6cf18b016cb9125c50e422c0 (diff) | |
download | gem5-e0074324bacf500f9d0cc11ebc6e2f29bf3d8ba1.tar.xz |
cpu: Probe points for basic PMU stats
This changeset adds probe points that can be used to implement PMU
counters for CPU stats. The following probes are supported:
* BaseCPU::ppCycles / Cycles
* BaseCPU::ppRetiredInsts / RetiredInsts
* BaseCPU::ppRetiredLoads / RetiredLoads
* BaseCPU::ppRetiredStores / RetiredStores
* BaseCPU::ppRetiredBranches RetiredBranches
Diffstat (limited to 'src/cpu/simple/timing.cc')
-rw-r--r-- | src/cpu/simple/timing.cc | 29 |
1 files changed, 18 insertions, 11 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 9a9714bee..84a2c09fd 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -178,7 +178,7 @@ TimingSimpleCPU::switchOut() assert(!stayAtPC); assert(microPC() == 0); - numCycles += curCycle() - previousCycle; + updateCycleCounts(); } @@ -332,8 +332,7 @@ TimingSimpleCPU::translationFault(const Fault &fault) { // fault may be NoFault in cases where a fault is suppressed, // for instance prefetches. - numCycles += curCycle() - previousCycle; - previousCycle = curCycle(); + updateCycleCounts(); if (traceData) { // Since there was a fault, we shouldn't trace this instruction. @@ -569,8 +568,7 @@ TimingSimpleCPU::fetch() _status = IcacheWaitResponse; completeIfetch(NULL); - numCycles += curCycle() - previousCycle; - previousCycle = curCycle(); + updateCycleCounts(); } } @@ -603,8 +601,7 @@ TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req, advanceInst(fault); } - numCycles += curCycle() - previousCycle; - previousCycle = curCycle(); + updateCycleCounts(); } @@ -651,8 +648,7 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt) _status = BaseSimpleCPU::Running; - numCycles += curCycle() - previousCycle; - previousCycle = curCycle(); + updateCycleCounts(); if (pkt) pkt->req->setAccessLatency(); @@ -753,8 +749,8 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt) pkt->req->getFlags().isSet(Request::NO_ACCESS)); pkt->req->setAccessLatency(); - numCycles += curCycle() - previousCycle; - previousCycle = curCycle(); + + updateCycleCounts(); if (pkt->senderState) { SplitFragmentSenderState * send_state = @@ -809,6 +805,17 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt) } void +TimingSimpleCPU::updateCycleCounts() +{ + const Cycles delta(curCycle() - previousCycle); + + numCycles += delta; + ppCycles->notify(delta); + + previousCycle = curCycle(); +} + +void TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) { TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask); |