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| author | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-09-20 17:18:35 -0400 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-09-20 17:18:35 -0400 |
| commit | e1403fc2af61c224c573c47c77a36f9b1b78e7df (patch) | |
| tree | 07647bb8697ac256d180bf8de35080eee2a63f3e /src/cpu/simple/timing.cc | |
| parent | 2b0438a11eb6a9640b06da91e8a300d0ac3ad81a (diff) | |
| download | gem5-e1403fc2af61c224c573c47c77a36f9b1b78e7df.tar.xz | |
alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate
activate(), suspend(), and halt() used on thread contexts had an optional
delay parameter. However this parameter was often ignored. Also, when used,
the delay was seemily arbitrarily set to 0 or 1 cycle (no other delays were
ever specified). This patch removes the delay parameter and 'Events'
associated with them across all ISAs and cores. Unused activate logic
is also removed.
Diffstat (limited to 'src/cpu/simple/timing.cc')
| -rw-r--r-- | src/cpu/simple/timing.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 9c8f8b57a..9a9714bee 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -200,9 +200,9 @@ TimingSimpleCPU::verifyMemoryMode() const } void -TimingSimpleCPU::activateContext(ThreadID thread_num, Cycles delay) +TimingSimpleCPU::activateContext(ThreadID thread_num) { - DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); + DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); assert(thread_num == 0); assert(thread); @@ -213,7 +213,7 @@ TimingSimpleCPU::activateContext(ThreadID thread_num, Cycles delay) _status = BaseSimpleCPU::Running; // kick things off by initiating the fetch of the next instruction - schedule(fetchEvent, clockEdge(delay)); + schedule(fetchEvent, clockEdge(Cycles(0))); } |