Merge ktlim@zizzer:/bk/newmem

into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem

--HG--
extra : convert_revision : d6bb87586cf7ee63ca32e36944c3755fae0b55d0

1 files changed, 8 insertions, 10 deletions

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 4d57bf6d5..abf316095 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -532,14 +532,13 @@ TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
 {
     if (pkt->isResponse()) {
         // delay processing of returned data until next CPU clock edge
-        Tick time = pkt->req->getTime();
-        while (time < curTick)
-            time += lat;
+        Tick mem_time = pkt->req->getTime();
+        Tick next_tick = cpu->nextCycle(mem_time);
 
-        if (time == curTick)
+        if (next_tick == curTick)
             cpu->completeIfetch(pkt);
         else
-            tickEvent.schedule(pkt, time);
+            tickEvent.schedule(pkt, next_tick);
 
         return true;
     }
@@ -610,14 +609,13 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
 {
     if (pkt->isResponse()) {
         // delay processing of returned data until next CPU clock edge
-        Tick time = pkt->req->getTime();
-        while (time < curTick)
-            time += lat;
+        Tick mem_time = pkt->req->getTime();
+        Tick next_tick = cpu->nextCycle(mem_time);
 
-        if (time == curTick)
+        if (next_tick == curTick)
             cpu->completeDataAccess(pkt);
         else
-            tickEvent.schedule(pkt, time);
+            tickEvent.schedule(pkt, next_tick);
 
         return true;
     }