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| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-02 22:34:51 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-02 22:34:51 -0500 |
| commit | 4e8d2d1593475008b926829e6944a59963166079 (patch) | |
| tree | 42ff01c4146f48c23179de7d2b01f4e6bdbe97d7 /src/cpu/simple/timing.cc | |
| parent | d8ada247f4fb107e7dc530ceb96a624d46c8ed9a (diff) | |
| download | gem5-4e8d2d1593475008b926829e6944a59963166079.tar.xz | |
make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way as the twin 64 bit loads
src/arch/isa_parser.py:
src/arch/sparc/isa/decoder.isa:
src/arch/sparc/isa/operands.isa:
src/base/bigint.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/mem/packet_access.hh:
make ldtw(a) Twin 32 bit load work correctly
--HG--
extra : convert_revision : 2646b269d58cc1774e896065875a56cf5e313b42
Diffstat (limited to 'src/cpu/simple/timing.cc')
| -rw-r--r-- | src/cpu/simple/timing.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index ff3606a74..7f857c68d 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -317,6 +317,10 @@ TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); template Fault +TimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); + +template +Fault TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); template |