Revert power patch sets with unexpected interactions

The following patches had unexpected interactions with the current
upstream code and have been reverted for now:

e07fd01651f3: power: Add support for power models
831c7f2f9e39: power: Low-power idle power state for idle CPUs
4f749e00b667: power: Add power states to ClockedObject

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>

--HG--
extra : amend_source : 0b6fb073c6bbc24be533ec431eb51fbf1b269508

1 files changed, 9 insertions, 9 deletions

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 515d6b23c..43f4eb9f4 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -218,8 +218,6 @@ TimingSimpleCPU::activateContext(ThreadID thread_num)
          == activeThreads.end()) {
         activeThreads.push_back(thread_num);
     }
-
-    BaseCPU::activateContext(thread_num);
 }
 
 
@@ -245,8 +243,6 @@ TimingSimpleCPU::suspendContext(ThreadID thread_num)
             deschedule(fetchEvent);
         }
     }
-
-    BaseCPU::suspendContext(thread_num);
 }
 
 bool
@@ -423,6 +419,7 @@ TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, unsigned flags)
 
     Fault fault;
     const int asid = 0;
+    const ThreadID tid = curThread;
     const Addr pc = thread->instAddr();
     unsigned block_size = cacheLineSize();
     BaseTLB::Mode mode = BaseTLB::Read;
@@ -430,8 +427,9 @@ TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, unsigned flags)
     if (traceData)
         traceData->setMem(addr, size, flags);
 
-    RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc,
-                                 thread->contextId());
+    RequestPtr req  = new Request(asid, addr, size,
+                                  flags, dataMasterId(), pc,
+                                  thread->contextId(), tid);
 
     req->taskId(taskId());
 
@@ -496,6 +494,7 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
 
     uint8_t *newData = new uint8_t[size];
     const int asid = 0;
+    const ThreadID tid = curThread;
     const Addr pc = thread->instAddr();
     unsigned block_size = cacheLineSize();
     BaseTLB::Mode mode = BaseTLB::Write;
@@ -511,8 +510,9 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
     if (traceData)
         traceData->setMem(addr, size, flags);
 
-    RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc,
-                                 thread->contextId());
+    RequestPtr req = new Request(asid, addr, size,
+                                 flags, dataMasterId(), pc,
+                                 thread->contextId(), tid);
 
     req->taskId(taskId());
 
@@ -614,7 +614,7 @@ TimingSimpleCPU::fetch()
         _status = BaseSimpleCPU::Running;
         Request *ifetch_req = new Request();
         ifetch_req->taskId(taskId());
-        ifetch_req->setContext(thread->contextId());
+        ifetch_req->setThreadContext(thread->contextId(), curThread);
         setupFetchRequest(ifetch_req);
         DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr());
         thread->itb->translateTiming(ifetch_req, thread->getTC(),