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author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-15 14:04:03 -0600 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-15 14:04:03 -0600 |
commit | 16f210da3715bb69bed9a80a5cf0eeffec0edf7c (patch) | |
tree | 16968d15dc37c4d38d1da459cacbcaa115a62a99 /src/cpu/simple/timing.cc | |
parent | 265e145db2d3675d2ac25fac975a21701f92fe50 (diff) | |
download | gem5-16f210da3715bb69bed9a80a5cf0eeffec0edf7c.tar.xz |
CPU: Fix bug when a split transaction is issued to a faster cache
In the case of a split transaction and a cache that is faster than a CPU we
could get two responses before next_tick expires. Add an event that is
scheduled in this case and return false rather than asserting.
Diffstat (limited to 'src/cpu/simple/timing.cc')
-rw-r--r-- | src/cpu/simple/timing.cc | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 2abe9cd59..7307f2fc9 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -999,7 +999,16 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) if (next_tick == curTick) { cpu->completeDataAccess(pkt); } else { - tickEvent.schedule(pkt, next_tick); + if (!tickEvent.scheduled()) { + tickEvent.schedule(pkt, next_tick); + } else { + // In the case of a split transaction and a cache that is + // faster than a CPU we could get two responses before + // next_tick expires + if (!retryEvent.scheduled()) + schedule(retryEvent, next_tick); + return false; + } } return true; |