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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-03-11 23:05:24 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-03-11 23:05:24 -0700 |
| commit | 61ff48a1f834b7335c2ae615a1f855995cfab335 (patch) | |
| tree | 82c725678c40d54be99ade3d3086a97f897a098c /src/cpu/simple/timing.cc | |
| parent | 17cb191c981ddb5a40f40a14a44e7b7ee7576c0d (diff) | |
| download | gem5-61ff48a1f834b7335c2ae615a1f855995cfab335.tar.xz | |
cpu: fix minor endian issue with trace output
(no functional change)
Diffstat (limited to 'src/cpu/simple/timing.cc')
| -rw-r--r-- | src/cpu/simple/timing.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index f398365d3..a8f86f8d2 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -564,7 +564,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) assert(split_addr <= addr || split_addr - addr < block_size); T *dataP = new T; - *dataP = TheISA::gtoh(data); + *dataP = TheISA::htog(data); _status = DTBWaitResponse; if (split_addr > addr) { RequestPtr req1, req2; |