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author | Anthony Gutierrez <atgutier@umich.edu> | 2012-08-15 10:38:08 -0400 |
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committer | Anthony Gutierrez <atgutier@umich.edu> | 2012-08-15 10:38:08 -0400 |
commit | 0b3897fc90901953e9d016466c37ab507f85023c (patch) | |
tree | 0e8b1fec8d7c4871686903d573e9fd0fd8734d1e /src/cpu/simple/timing.cc | |
parent | 5a648f2074caad8aee97e03f27e8eecc527a2cba (diff) | |
download | gem5-0b3897fc90901953e9d016466c37ab507f85023c.tar.xz |
O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs
This patch fixes some problems with the drain/switchout functionality
for the O3 cpu and for the ARM ISA and adds some useful debug print
statements.
This is an incremental fix as there are still a few bugs/mem leaks with the
switchout code. Particularly when switching from an O3CPU to a
TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA
I haven't encountered any more assertion failures; now the kernel will
typically panic inside of simulation.
Diffstat (limited to 'src/cpu/simple/timing.cc')
-rw-r--r-- | src/cpu/simple/timing.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index bae40eba4..6a9fe7efc 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -48,6 +48,7 @@ #include "cpu/simple/timing.hh" #include "cpu/exetrace.hh" #include "debug/Config.hh" +#include "debug/Drain.hh" #include "debug/ExecFaulting.hh" #include "debug/SimpleCPU.hh" #include "mem/packet.hh" @@ -129,6 +130,7 @@ TimingSimpleCPU::drain(Event *drain_event) } else { changeState(SimObject::Draining); drainEvent = drain_event; + DPRINTF(Drain, "CPU not drained\n"); return 1; } } @@ -829,7 +831,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt) void TimingSimpleCPU::completeDrain() { - DPRINTF(Config, "Done draining\n"); + DPRINTF(Drain, "CPU done draining, processing drain event\n"); changeState(SimObject::Drained); drainEvent->process(); } |