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authorAli Saidi <Ali.Saidi@ARM.com>2015-01-25 07:22:44 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2015-01-25 07:22:44 -0500
commit9d8ddd92dc99671db0706413b4f7a7d391d5f58c (patch)
tree6d06c4b9acb61fde848cf3c9fba75be643b39b81 /src/cpu/simple/timing.cc
parentf6742ea26e1a1cac21b486c7c5adad6fb6304e92 (diff)
downloadgem5-9d8ddd92dc99671db0706413b4f7a7d391d5f58c.tar.xz
sim: Clean up InstRecord
Track memory size and flags as well as add some comments and consts.
Diffstat (limited to 'src/cpu/simple/timing.cc')
-rw-r--r--src/cpu/simple/timing.cc10
1 files changed, 4 insertions, 6 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 8c90d7c4e..6de6899e7 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -402,9 +402,8 @@ TimingSimpleCPU::readMem(Addr addr, uint8_t *data,
unsigned block_size = cacheLineSize();
BaseTLB::Mode mode = BaseTLB::Read;
- if (traceData) {
- traceData->setAddr(addr);
- }
+ if (traceData)
+ traceData->setMem(addr, size, flags);
RequestPtr req = new Request(asid, addr, size,
flags, dataMasterId(), pc, _cpuId, tid);
@@ -479,9 +478,8 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
memcpy(newData, data, size);
}
- if (traceData) {
- traceData->setAddr(addr);
- }
+ if (traceData)
+ traceData->setMem(addr, size, flags);
RequestPtr req = new Request(asid, addr, size,
flags, dataMasterId(), pc, _cpuId, tid);