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author | Mitch Hayenga <mitch.hayenga@arm.com> | 2015-09-30 11:14:19 -0500 |
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committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2015-09-30 11:14:19 -0500 |
commit | 9e07a7504c94973e7837d1d3e96dbdb8d95cfad3 (patch) | |
tree | 7f845430119da24bcb4405df3a1c2102f6b7b534 /src/cpu/simple/timing.cc | |
parent | a5c4eb3de9deb3a71a6a5230a25ff5962e584980 (diff) | |
download | gem5-9e07a7504c94973e7837d1d3e96dbdb8d95cfad3.tar.xz |
cpu,isa,mem: Add per-thread wakeup logic
Changes wakeup functionality so that only specific threads on SMT
capable cpus are woken.
Diffstat (limited to 'src/cpu/simple/timing.cc')
-rw-r--r-- | src/cpu/simple/timing.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index f3241f7e5..6d67f610b 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -545,7 +545,7 @@ TimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) for (ThreadID tid = 0; tid < numThreads; tid++) { if (tid != sender) { if(getCpuAddrMonitor(tid)->doMonitor(pkt)) { - wakeup(); + wakeup(tid); } TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt, dcachePort.cacheBlockMask); @@ -865,7 +865,7 @@ TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) { for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { - cpu->wakeup(); + cpu->wakeup(tid); } } @@ -879,7 +879,7 @@ TimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt) { for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { if(cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { - cpu->wakeup(); + cpu->wakeup(tid); } } } |