CPU: Moving towards a more general port across CPU models

This patch performs minimal changes to move the instruction and data
ports from specialised subclasses to the base CPU (to the largest
degree possible). Ultimately it servers to make the CPU(s) have a
well-defined interface to the memory sub-system.

1 files changed, 3 insertions, 35 deletions

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 4375d2549..70583cae9 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -87,51 +87,19 @@ TimingSimpleCPU::init()
 #endif
 }
 
-Tick
-TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
-{
-    panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
-    return curTick();
-}
-
 void
-TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
-{
-    //No internal storage to update, jusst return
-    return;
-}
-
-void
-TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
-{
-    if (status == RangeChange) {
-        if (!snoopRangeSent) {
-            snoopRangeSent = true;
-            sendStatusChange(Port::RangeChange);
-        }
-        return;
-    }
-
-    panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
-}
-
-
-void
-TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
+TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
 {
     pkt = _pkt;
     cpu->schedule(this, t);
 }
 
 TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
-    : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this, p->clock),
-    dcachePort(this, p->clock), fetchEvent(this)
+    : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this),
+    dcachePort(this), fetchEvent(this)
 {
     _status = Idle;
 
-    icachePort.snoopRangeSent = false;
-    dcachePort.snoopRangeSent = false;
-
     ifetch_pkt = dcache_pkt = NULL;
     drainEvent = NULL;
     previousTick = 0;