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author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:25:42 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:25:42 -0700 |
commit | e056e49c4562108eeb7abbbeb1ee8acb096fe363 (patch) | |
tree | 162b440d59f688da34667ecf1add53bb4d52baf7 /src/cpu/simple/timing.cc | |
parent | 537239b278f7b8171d2eb09ef7f99c332266c48f (diff) | |
download | gem5-e056e49c4562108eeb7abbbeb1ee8acb096fe363.tar.xz |
Simple CPU: Make sure only instructions which complete without faulting are counted.
--HG--
extra : convert_revision : 01019c7129ed762d8826c3e6519989aa3fc3b5fd
Diffstat (limited to 'src/cpu/simple/timing.cc')
-rw-r--r-- | src/cpu/simple/timing.cc | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 70b774deb..046b2fe3b 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -540,13 +540,23 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt) delete dcache_pkt->req; delete dcache_pkt; dcache_pkt = NULL; + + // keep an instruction count + if (fault == NoFault) + countInst(); } + postExecute(); advanceInst(fault); } } else { // non-memory instruction: execute completely now Fault fault = curStaticInst->execute(this, traceData); + + // keep an instruction count + if (fault == NoFault) + countInst(); + postExecute(); advanceInst(fault); } @@ -615,6 +625,10 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt) Fault fault = curStaticInst->completeAcc(pkt, this, traceData); + // keep an instruction count + if (fault == NoFault) + countInst(); + if (pkt->isRead() && pkt->isLocked()) { TheISA::handleLockedRead(thread, pkt->req); } |