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author | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-10 15:00:41 -0500 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-10 15:00:41 -0500 |
commit | ef6dfc2983b3ef4d3c3cc6a2dff7f6f6f37cb691 (patch) | |
tree | a9bb9a4f0e1fb3ab182a73ff19e96bfbd0a9929a /src/cpu/simple/timing.cc | |
parent | dc4d47bad4f95501ebd144dc4aa53aa17563abcc (diff) | |
download | gem5-ef6dfc2983b3ef4d3c3cc6a2dff7f6f6f37cb691.tar.xz |
I thought this code got deleted, but since it hasn't I've moved it to a place where it doesn't access freed memory.
--HG--
extra : convert_revision : 4d9023f6193004a3e9cbeebd3721bccb50b2aab0
Diffstat (limited to 'src/cpu/simple/timing.cc')
-rw-r--r-- | src/cpu/simple/timing.cc | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 6f3604678..2e602648a 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -275,14 +275,14 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags) // memory system takes ownership of packet dcache_pkt = NULL; } + + // This will need a new way to tell if it has a dcache attached. + if (req->isUncacheable()) + recordEvent("Uncached Read"); } else { delete req; } - // This will need a new way to tell if it has a dcache attached. - if (req->isUncacheable()) - recordEvent("Uncached Read"); - return fault; } @@ -381,13 +381,13 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) dcache_pkt = NULL; } } + // This will need a new way to tell if it's hooked up to a cache or not. + if (req->isUncacheable()) + recordEvent("Uncached Write"); } else { delete req; } - // This will need a new way to tell if it's hooked up to a cache or not. - if (req->isUncacheable()) - recordEvent("Uncached Write"); // If the write needs to have a fault on the access, consider calling // changeStatus() and changing it to "bad addr write" or something. |