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| author | Ron Dreslinski <rdreslin@umich.edu> | 2006-11-14 01:10:36 -0500 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-11-14 01:10:36 -0500 |
| commit | 7babf6b3a89dffdef108c0d68057eabc491dcc50 (patch) | |
| tree | b7af0ebd30215c72d16cc44d81e7dcc86d036b3e /src/cpu/simple/timing.cc | |
| parent | 903a61871438fc872a4762e4d782264cbbd02154 (diff) | |
| download | gem5-7babf6b3a89dffdef108c0d68057eabc491dcc50.tar.xz | |
Make cpu's capable of having a phase shift
--HG--
extra : convert_revision : 7f082ba5c1cd2445aec731950c31a877aac23a75
Diffstat (limited to 'src/cpu/simple/timing.cc')
| -rw-r--r-- | src/cpu/simple/timing.cc | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 1ea2df894..d9839bede 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -169,7 +169,7 @@ TimingSimpleCPU::resume() fetchEvent = new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); - fetchEvent->schedule(curTick); + fetchEvent->schedule(nextCycle()); } changeState(SimObject::Running); @@ -241,7 +241,7 @@ TimingSimpleCPU::activateContext(int thread_num, int delay) // kick things off by initiating the fetch of the next instruction fetchEvent = new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); - fetchEvent->schedule(curTick + cycles(delay)); + fetchEvent->schedule(nextCycle(curTick + cycles(delay))); } @@ -683,6 +683,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) #endif // FULL_SYSTEM Param<int> clock; + Param<int> phase; Param<bool> defer_registration; Param<int> width; @@ -718,6 +719,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) #endif // FULL_SYSTEM INIT_PARAM(clock, "clock speed"), + INIT_PARAM_DFLT(phase, "clock phase", 0), INIT_PARAM(defer_registration, "defer system registration (for sampling)"), INIT_PARAM(width, "cpu width"), INIT_PARAM(function_trace, "Enable function trace"), @@ -739,6 +741,7 @@ CREATE_SIM_OBJECT(TimingSimpleCPU) params->progress_interval = progress_interval; params->deferRegistration = defer_registration; params->clock = clock; + params->phase = phase; params->functionTrace = function_trace; params->functionTraceStart = function_trace_start; params->system = system; |