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authorStephen Hines <hines@cs.fsu.edu>2008-02-05 23:44:13 -0500
committerStephen Hines <hines@cs.fsu.edu>2008-02-05 23:44:13 -0500
commit0ccf9a2c3751f160d7d51153ef468a60b4daf8d0 (patch)
tree3f5d77b729818492d27996adbc69b472f6fd4da7 /src/cpu/simple/timing.cc
parentca313e23033cd3f2ef827edf9a442ed1ae3d087f (diff)
downloadgem5-0ccf9a2c3751f160d7d51153ef468a60b4daf8d0.tar.xz
Add base ARM code to M5
--HG-- extra : convert_revision : d811bf87d1a0bfc712942ecd3db1b48fc75257af
Diffstat (limited to 'src/cpu/simple/timing.cc')
-rw-r--r--src/cpu/simple/timing.cc14
1 files changed, 10 insertions, 4 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index fc35f2666..e1fc6882f 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -598,13 +598,19 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
assert(fault == NoFault);
} else {
if (fault == NoFault) {
+ // Note that ARM can have NULL packets if the instruction gets
+ // squashed due to predication
// early fail on store conditional: complete now
- assert(dcache_pkt != NULL);
+ assert(dcache_pkt != NULL || THE_ISA == ARM_ISA);
+
fault = curStaticInst->completeAcc(dcache_pkt, this,
traceData);
- delete dcache_pkt->req;
- delete dcache_pkt;
- dcache_pkt = NULL;
+ if (dcache_pkt != NULL)
+ {
+ delete dcache_pkt->req;
+ delete dcache_pkt;
+ dcache_pkt = NULL;
+ }
// keep an instruction count
if (fault == NoFault)