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authorLisa Hsu <hsul@eecs.umich.edu>2008-11-02 21:56:57 -0500
committerLisa Hsu <hsul@eecs.umich.edu>2008-11-02 21:56:57 -0500
commitc55a467a06eaa59c47c52a2adddc266b8e545589 (patch)
treee86f0c75e6009285507cd2414b829c122bb0be1f /src/cpu/simple/timing.cc
parentf4bceb9760c93d3b5ff3c2606f7e460b42724670 (diff)
downloadgem5-c55a467a06eaa59c47c52a2adddc266b8e545589.tar.xz
make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch.
Diffstat (limited to 'src/cpu/simple/timing.cc')
-rw-r--r--src/cpu/simple/timing.cc15
1 files changed, 7 insertions, 8 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index a6059f55f..247899ca8 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -57,13 +57,12 @@ void
TimingSimpleCPU::init()
{
BaseCPU::init();
- cpuId = tc->readCpuId();
#if FULL_SYSTEM
for (int i = 0; i < threadContexts.size(); ++i) {
ThreadContext *tc = threadContexts[i];
// initialize CPU, including PC
- TheISA::initCPU(tc, cpuId);
+ TheISA::initCPU(tc, _cpuId);
}
#endif
}
@@ -203,7 +202,7 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
_status = Idle;
}
assert(threadContexts.size() == 1);
- cpuId = tc->readCpuId();
+ _cpuId = tc->cpuId();
previousTick = curTick;
}
@@ -250,7 +249,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
{
Request *req =
new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
- cpuId, /* thread ID */ 0);
+ _cpuId, /* thread ID */ 0);
if (traceData) {
traceData->setAddr(req->getVaddr());
@@ -301,7 +300,7 @@ TimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr,
int size, unsigned flags)
{
Request *req =
- new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0);
+ new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0);
if (traceData) {
traceData->setAddr(vaddr);
@@ -373,7 +372,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
Request *req =
new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
- cpuId, /* thread ID */ 0);
+ _cpuId, /* thread ID */ 0);
if (traceData) {
traceData->setAddr(req->getVaddr());
@@ -442,7 +441,7 @@ TimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr,
int size, unsigned flags)
{
Request *req =
- new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0);
+ new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0);
if (traceData) {
traceData->setAddr(vaddr);
@@ -528,7 +527,7 @@ TimingSimpleCPU::fetch()
if (!fromRom) {
Request *ifetch_req = new Request();
- ifetch_req->setThreadContext(cpuId, /* thread ID */ 0);
+ ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
Fault fault = setupFetchRequest(ifetch_req);
ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);