diff options
author | Ali Saidi <saidi@eecs.umich.edu> | 2006-07-20 19:00:40 -0400 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2006-07-20 19:00:40 -0400 |
commit | e8a329507566a6de71d5b60250f48d1ce6fa44fe (patch) | |
tree | 9fde84fddc1b106e255a0340de5767cc6a983c07 /src/cpu/simple/timing.cc | |
parent | 15e5ce96c76a20b9b27e5f7d7ed29e962422ad1a (diff) | |
download | gem5-e8a329507566a6de71d5b60250f48d1ce6fa44fe.tar.xz |
Enforce the timing cpu ticking at it's clock rate
Add a max time option in seconds and a single system root clock be 1THz
configs/test/fs.py:
Add a max time option in seconds and a single system root clock be 1THz
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
Enforce the timing cpu ticking at it's clock rate
--HG--
extra : convert_revision : a1b0de27abde867f9c3da5bec11639e3d82a95f5
Diffstat (limited to 'src/cpu/simple/timing.cc')
-rw-r--r-- | src/cpu/simple/timing.cc | 43 |
1 files changed, 40 insertions, 3 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 246bcec05..5c1654f7e 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -85,8 +85,16 @@ TimingSimpleCPU::CpuPort::recvStatusChange(Status status) panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); } + +void +TimingSimpleCPU::CpuPort::TickEvent::schedule(Packet *_pkt, Tick t) +{ + pkt = _pkt; + Event::schedule(t); +} + TimingSimpleCPU::TimingSimpleCPU(Params *p) - : BaseSimpleCPU(p), icachePort(this), dcachePort(this) + : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock) { _status = Idle; ifetch_pkt = dcache_pkt = NULL; @@ -462,11 +470,26 @@ TimingSimpleCPU::completeIfetch(Packet *pkt) } } +void +TimingSimpleCPU::IcachePort::ITickEvent::process() +{ + cpu->completeIfetch(pkt); +} bool TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt) { - cpu->completeIfetch(pkt); + // These next few lines could be replaced with something faster + // who knows what though + Tick time = pkt->req->getTime(); + while (time < curTick) + time += lat; + + if (time == curTick) + cpu->completeIfetch(pkt); + else + tickEvent.schedule(pkt, time); + return true; } @@ -523,11 +546,25 @@ TimingSimpleCPU::completeDrain() bool TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) { - cpu->completeDataAccess(pkt); + Tick time = pkt->req->getTime(); + while (time < curTick) + time += lat; + + if (time == curTick) + cpu->completeDataAccess(pkt); + else + tickEvent.schedule(pkt, time); + return true; } void +TimingSimpleCPU::DcachePort::DTickEvent::process() +{ + cpu->completeDataAccess(pkt); +} + +void TimingSimpleCPU::DcachePort::recvRetry() { // we shouldn't get a retry unless we have a packet that we're |