diff options
author | Mitch Hayenga <mitch.hayenga@arm.com> | 2015-09-30 11:14:19 -0500 |
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committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2015-09-30 11:14:19 -0500 |
commit | fafa83ed32933fe250d34dfca23fba348429b176 (patch) | |
tree | 3bf8fd636f1e879273045fefda3b5d7319a38479 /src/cpu/simple/timing.cc | |
parent | 582a0148b441fe9f4a6f977094c5ce6bf7ab6313 (diff) | |
download | gem5-fafa83ed32933fe250d34dfca23fba348429b176.tar.xz |
cpu: Add per-thread monitors
Adds per-thread address monitors to support FullSystem SMT.
Diffstat (limited to 'src/cpu/simple/timing.cc')
-rw-r--r-- | src/cpu/simple/timing.cc | 28 |
1 files changed, 22 insertions, 6 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 487da36ea..f3241f7e5 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -302,6 +302,7 @@ TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res, if (do_access) { dcache_pkt = pkt; handleWritePacket(); + threadSnoop(pkt, curThread); } else { _status = DcacheWaitResponse; completeDataAccess(pkt); @@ -538,6 +539,19 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, return NoFault; } +void +TimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) +{ + for (ThreadID tid = 0; tid < numThreads; tid++) { + if (tid != sender) { + if(getCpuAddrMonitor(tid)->doMonitor(pkt)) { + wakeup(); + } + TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt, + dcachePort.cacheBlockMask); + } + } +} void TimingSimpleCPU::finishTranslation(WholeTranslationState *state) @@ -849,9 +863,10 @@ TimingSimpleCPU::updateCycleCounts() void TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) { - // X86 ISA: Snooping an invalidation for monitor/mwait - if(cpu->getCpuAddrMonitor()->doMonitor(pkt)) { - cpu->wakeup(); + for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { + if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { + cpu->wakeup(); + } } for (auto &t_info : cpu->threadInfo) { @@ -862,9 +877,10 @@ TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt) void TimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt) { - // X86 ISA: Snooping an invalidation for monitor/mwait - if(cpu->getCpuAddrMonitor()->doMonitor(pkt)) { - cpu->wakeup(); + for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { + if(cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { + cpu->wakeup(); + } } } |