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| author | Ali Saidi <saidi@eecs.umich.edu> | 2008-07-01 10:24:16 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2008-07-01 10:24:16 -0400 |
| commit | 50e3e50e1ac592b357a47eecdc3c99a528172870 (patch) | |
| tree | 1ee6c72dc10691ac920e793646e38c73049f3a8f /src/cpu/simple/timing.cc | |
| parent | 9bd0bfe559d8c9633c5686ccf100ab921eb6eda2 (diff) | |
| download | gem5-50e3e50e1ac592b357a47eecdc3c99a528172870.tar.xz | |
Make the cached virtPort have a thread context so it can do everything that a newly created one can.
Diffstat (limited to 'src/cpu/simple/timing.cc')
| -rw-r--r-- | src/cpu/simple/timing.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 2cf7d584d..b86d4b2d7 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -766,7 +766,7 @@ TimingSimpleCPU::DcachePort::setPeer(Port *port) #if FULL_SYSTEM // Update the ThreadContext's memory ports (Functional/Virtual // Ports) - cpu->tcBase()->connectMemPorts(); + cpu->tcBase()->connectMemPorts(cpu->tcBase()); #endif } |