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| author | Steve Reinhardt <stever@gmail.com> | 2008-01-02 13:46:22 -0800 |
|---|---|---|
| committer | Steve Reinhardt <stever@gmail.com> | 2008-01-02 13:46:22 -0800 |
| commit | cde5a79eab22a3f6f10ebc68f24260721c98790f (patch) | |
| tree | 008ab1f1fc7ce5a0397490be9028c7ce47999f1d /src/cpu/simple/timing.cc | |
| parent | 3952e41ab1f1dfaa2f97a6a486528e4ea0bfc5a1 (diff) | |
| download | gem5-cde5a79eab22a3f6f10ebc68f24260721c98790f.tar.xz | |
Additional comments and helper functions for PrintReq.
--HG--
extra : convert_revision : 7eadf9b7db8c0289480f771271b6efe2400006d4
Diffstat (limited to 'src/cpu/simple/timing.cc')
| -rw-r--r-- | src/cpu/simple/timing.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 2f3ee5c73..fc35f2666 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -822,6 +822,13 @@ TimingSimpleCPU::IprEvent::description() } +void +TimingSimpleCPU::printAddr(Addr a) +{ + dcachePort.printAddr(a); +} + + //////////////////////////////////////////////////////////////////////// // // TimingSimpleCPU Simulation Object |