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author | Jose Marinho <jose.marinho@arm.com> | 2017-07-20 14:57:39 +0100 |
---|---|---|
committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-11-21 17:09:18 +0000 |
commit | 760cc5735f48f3a5a52ebe31df0c039b23c3d611 (patch) | |
tree | da4103b240221359838888467ac4f12544acc2c5 /src/cpu/simple/timing.cc | |
parent | 00232a868e4816d19c129fb3d6ef5519d7176d5a (diff) | |
download | gem5-760cc5735f48f3a5a52ebe31df0c039b23c3d611.tar.xz |
cpu, cpu, sim: move Cycle probe update
Move the code responsible for performing the actual probe point notify
into BaseCPU. Use BaseCPU activateContext and suspendContext to keep
track of sleep cycles. Create a probe point (ppActiveCycles) that does
not count cycles where the processor was asleep. Rename ppCycles
to ppAllCycles to reflect its nature.
Change-Id: I1907ddd07d0ff9f2ef22cc9f61f5f46c630c9d66
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5762
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu/simple/timing.cc')
-rw-r--r-- | src/cpu/simple/timing.cc | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index f57354d56..c38f2107f 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -185,6 +185,7 @@ TimingSimpleCPU::switchOut() assert(thread->microPC() == 0); updateCycleCounts(); + updateCycleCounters(BaseCPU::CPU_STATE_ON); } @@ -363,6 +364,7 @@ TimingSimpleCPU::translationFault(const Fault &fault) // fault may be NoFault in cases where a fault is suppressed, // for instance prefetches. updateCycleCounts(); + updateCycleCounters(BaseCPU::CPU_STATE_ON); if (traceData) { // Since there was a fault, we shouldn't trace this instruction. @@ -631,6 +633,7 @@ TimingSimpleCPU::fetch() completeIfetch(NULL); updateCycleCounts(); + updateCycleCounters(BaseCPU::CPU_STATE_ON); } } @@ -664,6 +667,7 @@ TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req, } updateCycleCounts(); + updateCycleCounters(BaseCPU::CPU_STATE_ON); } @@ -721,6 +725,7 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt) _status = BaseSimpleCPU::Running; updateCycleCounts(); + updateCycleCounters(BaseCPU::CPU_STATE_ON); if (pkt) pkt->req->setAccessLatency(); @@ -821,6 +826,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt) pkt->req->setAccessLatency(); updateCycleCounts(); + updateCycleCounters(BaseCPU::CPU_STATE_ON); if (pkt->senderState) { SplitFragmentSenderState * send_state = @@ -875,7 +881,6 @@ TimingSimpleCPU::updateCycleCounts() const Cycles delta(curCycle() - previousCycle); numCycles += delta; - ppCycles->notify(delta); previousCycle = curCycle(); } |