diff options
author | Mitch Hayenga <mitch.hayenga@arm.com> | 2016-04-05 12:39:21 -0500 |
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committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2016-04-05 12:39:21 -0500 |
commit | 8615b27174ae06db4665016c877b1e88031af203 (patch) | |
tree | 7b28888f71e7e41e84d4087b6ccb53670e04582b /src/cpu/simple/timing.cc | |
parent | 76ee011a12ade238d5cbf4b570e1d34d7ba72687 (diff) | |
download | gem5-8615b27174ae06db4665016c877b1e88031af203.tar.xz |
mem: Remove threadId from memory request class
In general, the ThreadID parameter is unnecessary in the memory system
as the ContextID is what is used for the purposes of locks/wakeups.
Since we allocate sequential ContextIDs for each thread on MT-enabled
CPUs, ThreadID is unnecessary as the CPUs can identify the requesting
thread through sideband info (SenderState / LSQ entries) or ContextID
offset from the base ContextID for a cpu.
Diffstat (limited to 'src/cpu/simple/timing.cc')
-rw-r--r-- | src/cpu/simple/timing.cc | 14 |
1 files changed, 5 insertions, 9 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index c99f9c475..515d6b23c 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -423,7 +423,6 @@ TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, unsigned flags) Fault fault; const int asid = 0; - const ThreadID tid = curThread; const Addr pc = thread->instAddr(); unsigned block_size = cacheLineSize(); BaseTLB::Mode mode = BaseTLB::Read; @@ -431,9 +430,8 @@ TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, unsigned flags) if (traceData) traceData->setMem(addr, size, flags); - RequestPtr req = new Request(asid, addr, size, - flags, dataMasterId(), pc, - thread->contextId(), tid); + RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc, + thread->contextId()); req->taskId(taskId()); @@ -498,7 +496,6 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, uint8_t *newData = new uint8_t[size]; const int asid = 0; - const ThreadID tid = curThread; const Addr pc = thread->instAddr(); unsigned block_size = cacheLineSize(); BaseTLB::Mode mode = BaseTLB::Write; @@ -514,9 +511,8 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, if (traceData) traceData->setMem(addr, size, flags); - RequestPtr req = new Request(asid, addr, size, - flags, dataMasterId(), pc, - thread->contextId(), tid); + RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc, + thread->contextId()); req->taskId(taskId()); @@ -618,7 +614,7 @@ TimingSimpleCPU::fetch() _status = BaseSimpleCPU::Running; Request *ifetch_req = new Request(); ifetch_req->taskId(taskId()); - ifetch_req->setThreadContext(thread->contextId(), curThread); + ifetch_req->setContext(thread->contextId()); setupFetchRequest(ifetch_req); DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); thread->itb->translateTiming(ifetch_req, thread->getTC(), |