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| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 04:00:35 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 04:00:35 -0500 |
| commit | f26a28929583f2ed7fb55521e49c3f9bef557c05 (patch) | |
| tree | e5d71fc69566b02a394015776b0f3f4e3be81427 /src/cpu/simple/timing.cc | |
| parent | 6ebe8d863ae0c5a7799e9421da32593ac35e1cc7 (diff) | |
| download | gem5-f26a28929583f2ed7fb55521e49c3f9bef557c05.tar.xz | |
mem: Split port retry for all different packet classes
This patch fixes a long-standing isue with the port flow
control. Before this patch the retry mechanism was shared between all
different packet classes. As a result, a snoop response could get
stuck behind a request waiting for a retry, even if the send/recv
functions were split. This caused message-dependent deadlocks in
stress-test scenarios.
The patch splits the retry into one per packet (message) class. Thus,
sendTimingReq has a corresponding recvReqRetry, sendTimingResp has
recvRespRetry etc. Most of the changes to the code involve simply
clarifying what type of request a specific object was accepting.
The biggest change in functionality is in the cache downstream packet
queue, facing the memory. This queue was shared by requests and snoop
responses, and it is now split into two queues, each with their own
flow control, but the same physical MasterPort. These changes fixes
the previously seen deadlocks.
Diffstat (limited to 'src/cpu/simple/timing.cc')
| -rw-r--r-- | src/cpu/simple/timing.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 9171395b0..8b95696a3 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -729,7 +729,7 @@ TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) } void -TimingSimpleCPU::IcachePort::recvRetry() +TimingSimpleCPU::IcachePort::recvReqRetry() { // we shouldn't get a retry unless we have a packet that we're // waiting to transmit @@ -846,8 +846,8 @@ TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) // In the case of a split transaction and a cache that is // faster than a CPU we could get two responses in the // same tick, delay the second one - if (!retryEvent.scheduled()) - cpu->schedule(retryEvent, cpu->clockEdge(Cycles(1))); + if (!retryRespEvent.scheduled()) + cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1))); return false; } } @@ -859,7 +859,7 @@ TimingSimpleCPU::DcachePort::DTickEvent::process() } void -TimingSimpleCPU::DcachePort::recvRetry() +TimingSimpleCPU::DcachePort::recvReqRetry() { // we shouldn't get a retry unless we have a packet that we're // waiting to transmit |