Significant rework of Packet class interface:

- new constructor guarantees initialization of most fields
- flags track status of non-guaranteed fields (addr, size, src)
- accessor functions (getAddr() etc.) check status on access
- Command & Result classes are nested in Packet class scope
- Command now built from vector of behavior bits
- string version of Command for tracing
- reinitFromRequest() and makeTimingResponse() encapsulate
common manipulations of existing packets

src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/timing.cc:
src/dev/alpha_console.cc:
src/dev/ide_ctrl.cc:
src/dev/io_device.cc:
src/dev/io_device.hh:
src/dev/isa_fake.cc:
src/dev/ns_gige.cc:
src/dev/pciconfigall.cc:
src/dev/sinic.cc:
src/dev/tsunami_cchip.cc:
src/dev/tsunami_io.cc:
src/dev/tsunami_pchip.cc:
src/dev/uart8250.cc:
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/physical.cc:
src/mem/port.cc:
src/mem/port.hh:
src/mem/request.hh:
    Update for new Packet interface.

--HG--
extra : convert_revision : 9973d09ea4fa61795f23772a7d3995fa4df5c269

1 files changed, 6 insertions, 18 deletions

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 70b88c4b1..d57935ed0 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -187,13 +187,9 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
 
     // Now do the access.
     if (fault == NoFault) {
-        Packet *data_read_pkt = new Packet;
-        data_read_pkt->cmd = Read;
-        data_read_pkt->req = data_read_req;
+        Packet *data_read_pkt =
+            new Packet(data_read_req, Packet::ReadReq, Packet::Broadcast);
         data_read_pkt->dataDynamic<T>(new T);
-        data_read_pkt->addr = data_read_req->getPaddr();
-        data_read_pkt->size = sizeof(T);
-        data_read_pkt->dest = Packet::Broadcast;
 
         if (!dcachePort.sendTiming(data_read_pkt)) {
             _status = DcacheRetry;
@@ -268,14 +264,10 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
     Fault fault = cpuXC->translateDataWriteReq(data_write_req);
     // Now do the access.
     if (fault == NoFault) {
-        Packet *data_write_pkt = new Packet;
-        data_write_pkt->cmd = Write;
-        data_write_pkt->req = data_write_req;
+        Packet *data_write_pkt =
+            new Packet(data_write_req, Packet::WriteReq, Packet::Broadcast);
         data_write_pkt->allocate();
-        data_write_pkt->size = sizeof(T);
         data_write_pkt->set(data);
-        data_write_pkt->addr = data_write_req->getPaddr();
-        data_write_pkt->dest = Packet::Broadcast;
 
         if (!dcachePort.sendTiming(data_write_pkt)) {
             _status = DcacheRetry;
@@ -350,12 +342,8 @@ TimingSimpleCPU::fetch()
     Request *ifetch_req = new Request(true);
     ifetch_req->setSize(sizeof(MachInst));
 
-    ifetch_pkt = new Packet;
-    ifetch_pkt->cmd = Read;
+    ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
     ifetch_pkt->dataStatic(&inst);
-    ifetch_pkt->req = ifetch_req;
-    ifetch_pkt->size = sizeof(MachInst);
-    ifetch_pkt->dest = Packet::Broadcast;
 
     Fault fault = setupFetchPacket(ifetch_pkt);
     if (fault == NoFault) {
@@ -441,7 +429,7 @@ TimingSimpleCPU::completeDataAccess(Packet *pkt)
 {
     // received a response from the dcache: complete the load or store
     // instruction
-    assert(pkt->result == Success);
+    assert(pkt->result == Packet::Success);
     assert(_status == DcacheWaitResponse);
     _status = Running;