summaryrefslogtreecommitdiff
path: root/src/cpu/simple/timing.hh
diff options
context:
space:
mode:
authorNathan Binkert <binkertn@umich.edu>2006-10-20 00:10:12 -0700
committerNathan Binkert <binkertn@umich.edu>2006-10-20 00:10:12 -0700
commita4c6f0d69eda5d23b12576080d532ddf768fbdbe (patch)
tree72863fc8729c977d15d1c60aeb8243407e964550 /src/cpu/simple/timing.hh
parent7245d4530d0c8367fa7b1adadcb55e1e8bd466e7 (diff)
downloadgem5-a4c6f0d69eda5d23b12576080d532ddf768fbdbe.tar.xz
Use PacketPtr everywhere
--HG-- extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711
Diffstat (limited to 'src/cpu/simple/timing.hh')
-rw-r--r--src/cpu/simple/timing.hh20
1 files changed, 10 insertions, 10 deletions
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 988ddeded..577e13e40 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -84,9 +84,9 @@ class TimingSimpleCPU : public BaseSimpleCPU
protected:
- virtual Tick recvAtomic(Packet *pkt);
+ virtual Tick recvAtomic(PacketPtr pkt);
- virtual void recvFunctional(Packet *pkt);
+ virtual void recvFunctional(PacketPtr pkt);
virtual void recvStatusChange(Status status);
@@ -96,13 +96,13 @@ class TimingSimpleCPU : public BaseSimpleCPU
struct TickEvent : public Event
{
- Packet *pkt;
+ PacketPtr pkt;
TimingSimpleCPU *cpu;
TickEvent(TimingSimpleCPU *_cpu)
:Event(&mainEventQueue), cpu(_cpu) {}
const char *description() { return "Timing CPU clock event"; }
- void schedule(Packet *_pkt, Tick t);
+ void schedule(PacketPtr _pkt, Tick t);
};
};
@@ -117,7 +117,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
protected:
- virtual bool recvTiming(Packet *pkt);
+ virtual bool recvTiming(PacketPtr pkt);
virtual void recvRetry();
@@ -144,7 +144,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
protected:
- virtual bool recvTiming(Packet *pkt);
+ virtual bool recvTiming(PacketPtr pkt);
virtual void recvRetry();
@@ -163,8 +163,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
IcachePort icachePort;
DcachePort dcachePort;
- Packet *ifetch_pkt;
- Packet *dcache_pkt;
+ PacketPtr ifetch_pkt;
+ PacketPtr dcache_pkt;
int cpu_id;
Tick previousTick;
@@ -192,8 +192,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
void fetch();
- void completeIfetch(Packet *);
- void completeDataAccess(Packet *);
+ void completeIfetch(PacketPtr );
+ void completeDataAccess(PacketPtr );
void advanceInst(Fault fault);
private:
void completeDrain();