diff options
| author | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-09-20 17:18:35 -0400 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2014-09-20 17:18:35 -0400 |
| commit | e1403fc2af61c224c573c47c77a36f9b1b78e7df (patch) | |
| tree | 07647bb8697ac256d180bf8de35080eee2a63f3e /src/cpu/simple/timing.hh | |
| parent | 2b0438a11eb6a9640b06da91e8a300d0ac3ad81a (diff) | |
| download | gem5-e1403fc2af61c224c573c47c77a36f9b1b78e7df.tar.xz | |
alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate
activate(), suspend(), and halt() used on thread contexts had an optional
delay parameter. However this parameter was often ignored. Also, when used,
the delay was seemily arbitrarily set to 0 or 1 cycle (no other delays were
ever specified). This patch removes the delay parameter and 'Events'
associated with them across all ISAs and cores. Unused activate logic
is also removed.
Diffstat (limited to 'src/cpu/simple/timing.hh')
| -rw-r--r-- | src/cpu/simple/timing.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index a7ea57c67..24f7002ff 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -271,7 +271,7 @@ class TimingSimpleCPU : public BaseSimpleCPU void verifyMemoryMode() const; - virtual void activateContext(ThreadID thread_num, Cycles delay); + virtual void activateContext(ThreadID thread_num); virtual void suspendContext(ThreadID thread_num); Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); |