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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-05-30 19:45:54 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-05-30 19:45:54 -0400 |
| commit | f0c05de9f98fe3c6e386d3f0346f183ce5abe6c8 (patch) | |
| tree | 15ce09bb61f953960bd77c388e76d63e0ae8b6c5 /src/cpu/simple/timing.hh | |
| parent | e371dc32a94b0c4ffe7192aad634b425b5b43437 (diff) | |
| parent | aa11330ddbb1e579aa241d01d24875cc9d86d5f8 (diff) | |
| download | gem5-f0c05de9f98fe3c6e386d3f0346f183ce5abe6c8.tar.xz | |
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-py
--HG--
extra : convert_revision : 36640569d33c4410320b8444bb572f408bf5edde
Diffstat (limited to 'src/cpu/simple/timing.hh')
| -rw-r--r-- | src/cpu/simple/timing.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index b46631d5a..cb37824bc 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -100,7 +100,7 @@ class TimingSimpleCPU : public BaseSimpleCPU virtual bool recvTiming(Packet *pkt); - virtual Packet *recvRetry(); + virtual void recvRetry(); }; class DcachePort : public CpuPort @@ -115,7 +115,7 @@ class TimingSimpleCPU : public BaseSimpleCPU virtual bool recvTiming(Packet *pkt); - virtual Packet *recvRetry(); + virtual void recvRetry(); }; IcachePort icachePort; |