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authorAli Saidi <Ali.Saidi@ARM.com>2014-01-24 15:29:30 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2014-01-24 15:29:30 -0600
commit6bed6e0352a68723ea55017b3e09a8c279af11ec (patch)
treef7fb2a163ea470144a424bf21a7dd578754546af /src/cpu/simple/timing.hh
parentd3444c6603afe38b00036292a854f52069b90a80 (diff)
downloadgem5-6bed6e0352a68723ea55017b3e09a8c279af11ec.tar.xz
cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped.
This patch add support for generating wake-up events in the CPU when an address that is currently in the exclusive state is hit by a snoop. This mechanism is required for ARMv8 multi-processor support.
Diffstat (limited to 'src/cpu/simple/timing.hh')
-rw-r--r--src/cpu/simple/timing.hh12
1 files changed, 10 insertions, 2 deletions
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 03264315e..4a5a20429 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -165,7 +165,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
/**
* Snooping a coherence request, do nothing.
*/
- virtual void recvTimingSnoopReq(PacketPtr pkt) { }
+ virtual void recvTimingSnoopReq(PacketPtr pkt) {}
TimingSimpleCPU* cpu;
@@ -217,10 +217,18 @@ class TimingSimpleCPU : public BaseSimpleCPU
DcachePort(TimingSimpleCPU *_cpu)
: TimingCPUPort(_cpu->name() + ".dcache_port", _cpu),
tickEvent(_cpu)
- { }
+ {
+ cacheBlockMask = ~(cpu->cacheLineSize() - 1);
+ }
+ Addr cacheBlockMask;
protected:
+ /** Snoop a coherence request, we need to check if this causes
+ * a wakeup event on a cpu that is monitoring an address
+ */
+ virtual void recvTimingSnoopReq(PacketPtr pkt);
+
virtual bool recvTimingResp(PacketPtr pkt);
virtual void recvRetry();