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authorGabe Black <gblack@eecs.umich.edu>2009-04-08 22:21:27 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-04-08 22:21:27 -0700
commit7b5a96f06b530db35637aca6f9d0f7a2ddfa6e60 (patch)
tree4c212f665de2628eac6f84d389de7a79b6d0b933 /src/cpu/simple/timing.hh
parent08043c777f1f05f5e14581950013461f328965be (diff)
downloadgem5-7b5a96f06b530db35637aca6f9d0f7a2ddfa6e60.tar.xz
tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
Diffstat (limited to 'src/cpu/simple/timing.hh')
-rw-r--r--src/cpu/simple/timing.hh6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index a02ec48c9..731eeeefc 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -106,7 +106,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
{}
void finish(Fault fault, RequestPtr req,
- ThreadContext *tc, bool write)
+ ThreadContext *tc, bool write, bool execute)
{
cpu->sendFetch(fault, req, tc);
}
@@ -129,7 +129,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
void
finish(Fault fault, RequestPtr req,
- ThreadContext *tc, bool write)
+ ThreadContext *tc, bool write, bool execute)
{
cpu->sendData(fault, req, data, res, read);
delete this;
@@ -173,7 +173,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
void
finish(Fault fault, RequestPtr req,
- ThreadContext *tc, bool write)
+ ThreadContext *tc, bool write, bool execute)
{
assert(state);
assert(state->outstanding);