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authorGabe Black <gblack@eecs.umich.edu>2010-08-13 06:16:02 -0700
committerGabe Black <gblack@eecs.umich.edu>2010-08-13 06:16:02 -0700
commitaa8c6e9c959eab4d516bc07593bea20ade9ad80c (patch)
tree3e0112e567da5dc1aa019f85458fbd9e37ad0cf2 /src/cpu/simple/timing.hh
parent65dbcc6ea170e05ca2370a9a265a61668250fa98 (diff)
downloadgem5-aa8c6e9c959eab4d516bc07593bea20ade9ad80c.tar.xz
CPU: Add readBytes and writeBytes functions to the exec contexts.
Diffstat (limited to 'src/cpu/simple/timing.hh')
-rw-r--r--src/cpu/simple/timing.hh10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 62c105418..65cbe3098 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -251,9 +251,14 @@ class TimingSimpleCPU : public BaseSimpleCPU
template <class T>
Fault read(Addr addr, T &data, unsigned flags);
+ Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+
template <class T>
Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
+ Fault writeBytes(uint8_t *data, unsigned size,
+ Addr addr, unsigned flags, uint64_t *res);
+
void fetch();
void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
void completeIfetch(PacketPtr );
@@ -274,6 +279,11 @@ class TimingSimpleCPU : public BaseSimpleCPU
private:
+ // The backend for writeBytes and write. It's the same as writeBytes, but
+ // doesn't make a copy of data.
+ Fault writeTheseBytes(uint8_t *data, unsigned size,
+ Addr addr, unsigned flags, uint64_t *res);
+
typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
FetchEvent fetchEvent;