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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-15 14:04:03 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-15 14:04:03 -0600 |
| commit | 16f210da3715bb69bed9a80a5cf0eeffec0edf7c (patch) | |
| tree | 16968d15dc37c4d38d1da459cacbcaa115a62a99 /src/cpu/simple/timing.hh | |
| parent | 265e145db2d3675d2ac25fac975a21701f92fe50 (diff) | |
| download | gem5-16f210da3715bb69bed9a80a5cf0eeffec0edf7c.tar.xz | |
CPU: Fix bug when a split transaction is issued to a faster cache
In the case of a split transaction and a cache that is faster than a CPU we
could get two responses before next_tick expires. Add an event that is
scheduled in this case and return false rather than asserting.
Diffstat (limited to 'src/cpu/simple/timing.hh')
| -rw-r--r-- | src/cpu/simple/timing.hh | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index 65cbe3098..2b0c8942a 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -140,7 +140,7 @@ class TimingSimpleCPU : public BaseSimpleCPU public: CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat) - : Port(_name, _cpu), cpu(_cpu), lat(_lat) + : Port(_name, _cpu), cpu(_cpu), lat(_lat), retryEvent(this) { } bool snoopRangeSent; @@ -161,12 +161,14 @@ class TimingSimpleCPU : public BaseSimpleCPU { PacketPtr pkt; TimingSimpleCPU *cpu; + CpuPort *port; TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {} const char *description() const { return "Timing CPU tick"; } void schedule(PacketPtr _pkt, Tick t); }; + EventWrapper<Port, &Port::sendRetry> retryEvent; }; class IcachePort : public CpuPort |