Various fixes for the CPU models to support the features that have been moved to python.

src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/simple/atomic.hh:
    Switching out no longer takes a sampler.
src/cpu/simple/atomic.cc:
    Fix up switching out.  Also fix up serialization; the nameOut() was messing up the ordering.
src/cpu/simple/timing.cc:
    Add in quiesce, fix up serialization.
src/cpu/simple/timing.hh:
    Add in queisce, fix up serialization.

--HG--
extra : convert_revision : 9d59d53bdf269d4d82fb119e5ae7c8a5d475880b

1 files changed, 9 insertions, 1 deletions

diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index ab0b2d2ca..d91144e4a 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -64,6 +64,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
     Status status() const { return _status; }
 
+    Event *quiesceEvent;
+
   private:
 
     class CpuPort : public Port
@@ -131,7 +133,11 @@ class TimingSimpleCPU : public BaseSimpleCPU
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
-    void switchOut(Sampler *s);
+    virtual bool quiesce(Event *quiesce_event);
+    virtual void resume();
+    virtual void setMemoryMode(State new_mode);
+
+    void switchOut();
     void takeOverFrom(BaseCPU *oldCPU);
 
     virtual void activateContext(int thread_num, int delay);
@@ -147,6 +153,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
     void completeIfetch(Packet *);
     void completeDataAccess(Packet *);
     void advanceInst(Fault fault);
+  private:
+    void completeQuiesce();
 };
 
 #endif // __CPU_SIMPLE_TIMING_HH__