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author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-05-26 14:33:43 -0400 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-05-26 14:33:43 -0400 |
commit | 53510f184452c46868a9e6ece9ccb7f30ab70843 (patch) | |
tree | cef0d8930a7679e5b8e3c097dda0774386cf3c0d /src/cpu/simple/timing.hh | |
parent | acb05ebcf6b6a9891ab856c466bd128f1ea62128 (diff) | |
download | gem5-53510f184452c46868a9e6ece9ccb7f30ab70843.tar.xz |
Fixes for TimingSimpleCPU under full system. Now boots Alpha Linux!
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
Move traceData->finalize() into postExecute().
src/cpu/simple/timing.cc:
Fixes for full system. Now boots Alpha Linux!
- Handle ifetch faults, suspend/resume.
- Delete memory request & packet objects on response.
- Don't try to do split memory accesses on prefetch references
(ISA description doesn't support this).
src/cpu/simple/timing.hh:
Minor reorganization of internal methods.
--HG--
extra : convert_revision : 59e3ee5e4cb53c424ebdbe2e504d97e88c08a978
Diffstat (limited to 'src/cpu/simple/timing.hh')
-rw-r--r-- | src/cpu/simple/timing.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index 7f38e629a..b46631d5a 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -142,9 +142,9 @@ class TimingSimpleCPU : public BaseSimpleCPU Fault write(T data, Addr addr, unsigned flags, uint64_t *res); void fetch(); - void completeInst(Fault fault); - void completeIfetch(); + void completeIfetch(Packet *); void completeDataAccess(Packet *); + void advanceInst(Fault fault); }; #endif // __CPU_SIMPLE_TIMING_HH__ |