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authorGiacomo Travaglini <giacomo.travaglini@arm.com>2018-06-04 09:40:19 +0100
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2018-06-11 16:55:30 +0000
commitf54020eb8155371725ab75b0fc5c419287eca084 (patch)
tree65d379f7603e689e083e9a58ff4c2e90abd19fbf /src/cpu/simple/timing.hh
parent2113b21996d086dab32b9fd388efe3df241bfbd2 (diff)
downloadgem5-f54020eb8155371725ab75b0fc5c419287eca084.tar.xz
misc: Using smart pointers for memory Requests
This patch is changing the underlying type for RequestPtr from Request* to shared_ptr<Request>. Having memory requests being managed by smart pointers will simplify the code; it will also prevent memory leakage and dangling pointers. Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10996 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/cpu/simple/timing.hh')
-rw-r--r--src/cpu/simple/timing.hh16
1 files changed, 10 insertions, 6 deletions
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 8498630b4..0300d38eb 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -124,7 +124,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
}
void
- finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
+ finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
BaseTLB::Mode mode)
{
cpu->sendFetch(fault, req, tc);
@@ -133,15 +133,18 @@ class TimingSimpleCPU : public BaseSimpleCPU
FetchTranslation fetchTranslation;
void threadSnoop(PacketPtr pkt, ThreadID sender);
- void sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read);
- void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req,
+ void sendData(const RequestPtr &req,
+ uint8_t *data, uint64_t *res, bool read);
+ void sendSplitData(const RequestPtr &req1, const RequestPtr &req2,
+ const RequestPtr &req,
uint8_t *data, bool read);
void translationFault(const Fault &fault);
- PacketPtr buildPacket(RequestPtr req, bool read);
+ PacketPtr buildPacket(const RequestPtr &req, bool read);
void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
- RequestPtr req1, RequestPtr req2, RequestPtr req,
+ const RequestPtr &req1, const RequestPtr &req2,
+ const RequestPtr &req,
uint8_t *data, bool read);
bool handleReadPacket(PacketPtr pkt);
@@ -289,7 +292,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
Addr addr, Request::Flags flags, uint64_t *res) override;
void fetch();
- void sendFetch(const Fault &fault, RequestPtr req, ThreadContext *tc);
+ void sendFetch(const Fault &fault,
+ const RequestPtr &req, ThreadContext *tc);
void completeIfetch(PacketPtr );
void completeDataAccess(PacketPtr pkt);
void advanceInst(const Fault &fault);