CPU: Refactor read/write in the simple timing CPU.

1 files changed, 4 insertions, 6 deletions

diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index b641b1302..c305d0361 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -65,12 +65,6 @@ class TimingSimpleCPU : public BaseSimpleCPU
         int outstanding;
         PacketPtr fragments[2];
 
-        SplitMainSenderState()
-        {
-            fragments[0] = NULL;
-            fragments[1] = NULL;
-        }
-
         int
         getPendingFragment()
         {
@@ -102,6 +96,10 @@ class TimingSimpleCPU : public BaseSimpleCPU
         }
     };
 
+    Fault buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, RequestPtr &req,
+            Addr split_addr, uint8_t *data, bool read);
+    Fault buildPacket(PacketPtr &pkt, RequestPtr &req, bool read);
+
     bool handleReadPacket(PacketPtr pkt);
     // This function always implicitly uses dcache_pkt.
     bool handleWritePacket();