diff options
author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-10-08 10:53:24 -0700 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-10-08 10:53:24 -0700 |
commit | d3fba5aa30adfb006b99895e869ed175213d0134 (patch) | |
tree | 461b216e3efae357acc2939fcc17d67bd5903e7c /src/cpu/simple/timing.hh | |
parent | be36c808f77cfcb001aacb8cb32f45fb5909e00e (diff) | |
download | gem5-d3fba5aa30adfb006b99895e869ed175213d0134.tar.xz |
Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory. *No* support for caches or O3CPU.
Note that properly setting cpu_id on all CPUs is now required
for correct operation.
src/arch/SConscript:
src/base/traceflags.py:
src/cpu/base.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
src/python/m5/objects/BaseCPU.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory. *No* support for caches or O3CPU.
--HG--
extra : convert_revision : 6ce982d44924cc477e049b9adf359818908e72be
Diffstat (limited to 'src/cpu/simple/timing.hh')
-rw-r--r-- | src/cpu/simple/timing.hh | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index d03fa4bc0..b65eebd99 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -166,6 +166,8 @@ class TimingSimpleCPU : public BaseSimpleCPU Packet *ifetch_pkt; Packet *dcache_pkt; + int cpu_id; + public: virtual Port *getPort(const std::string &if_name, int idx = -1); |