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| author | Andreas Sandberg <andreas@sandberg.pp.se> | 2015-11-27 14:41:59 +0000 |
|---|---|---|
| committer | Andreas Sandberg <andreas@sandberg.pp.se> | 2015-11-27 14:41:59 +0000 |
| commit | 5383e1ada49b59daf4ff8703076923d4ccb6207d (patch) | |
| tree | 3a3dd8f95be7cf5546a5c2d1e4e58107ae2c03a0 /src/cpu/simple | |
| parent | fed0ea55c476d9843e3f07e4f879254d34d99279 (diff) | |
| download | gem5-5383e1ada49b59daf4ff8703076923d4ccb6207d.tar.xz | |
base: Add support for changing output directories
This changeset adds support for changing the simulator output
directory. This can be useful when the simulation goes through several
stages (e.g., a warming phase, a simulation phase, and a verification
phase) since it allows the output from each stage to be located in a
different directory. Relocation is done by calling core.setOutputDir()
from Python or simout.setOutputDirectory() from C++.
This change affects several parts of the design of the gem5's output
subsystem. First, files returned by an OutputDirectory instance (e.g.,
simout) are of the type OutputStream instead of a std::ostream. This
allows us to do some more book keeping and control re-opening of files
when the output directory is changed. Second, new subdirectories are
OutputDirectory instances, which should be used to create files in
that sub-directory.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
[sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version]
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu/simple')
| -rw-r--r-- | src/cpu/simple/probes/simpoint.cc | 6 | ||||
| -rw-r--r-- | src/cpu/simple/probes/simpoint.hh | 3 |
2 files changed, 5 insertions, 4 deletions
diff --git a/src/cpu/simple/probes/simpoint.cc b/src/cpu/simple/probes/simpoint.cc index 2de3cd420..4f4b5da39 100644 --- a/src/cpu/simple/probes/simpoint.cc +++ b/src/cpu/simple/probes/simpoint.cc @@ -126,13 +126,13 @@ SimPoint::profile(const std::pair<SimpleThread*, StaticInstPtr>& p) std::sort(counts.begin(), counts.end()); // Print output BBV info - *simpointStream << "T"; + *simpointStream->stream() << "T"; for (auto cnt_itr = counts.begin(); cnt_itr != counts.end(); ++cnt_itr) { - *simpointStream << ":" << cnt_itr->first + *simpointStream->stream() << ":" << cnt_itr->first << ":" << cnt_itr->second << " "; } - *simpointStream << "\n"; + *simpointStream->stream() << "\n"; intervalDrift = (intervalCount + intervalDrift) - intervalSize; intervalCount = 0; diff --git a/src/cpu/simple/probes/simpoint.hh b/src/cpu/simple/probes/simpoint.hh index 2f4ed080d..2873ae410 100644 --- a/src/cpu/simple/probes/simpoint.hh +++ b/src/cpu/simple/probes/simpoint.hh @@ -43,6 +43,7 @@ #include <unordered_map> +#include "base/output.hh" #include "cpu/simple_thread.hh" #include "params/SimPoint.hh" #include "sim/probe/probe.hh" @@ -97,7 +98,7 @@ class SimPoint : public ProbeListenerObject /** Excess inst count from previous interval*/ uint64_t intervalDrift; /** Pointer to SimPoint BBV output stream */ - std::ostream *simpointStream; + OutputStream *simpointStream; /** Basic Block information */ struct BBInfo { |