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author | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:30 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:30 -0400 |
commit | 7a61f667f072bace1efb38e7c0d5fc49e4e0b420 (patch) | |
tree | 1281cab9ddd3f4c919180491c6b68715628606ab /src/cpu/simple | |
parent | f7d44590cb5455c2b70c2b26005bbbcdd771de18 (diff) | |
download | gem5-7a61f667f072bace1efb38e7c0d5fc49e4e0b420.tar.xz |
cpu: Fix timing CPU drain check
This patch modifies the SimpleTimingCPU drain check to also consider
the fetch event. Previously, there was an assumption that there is
never a fetch event scheduled if the CPU is not executing
microcode. However, when a context is activated, a fetch even is
scheduled, and microPC() is zero.
Diffstat (limited to 'src/cpu/simple')
-rw-r--r-- | src/cpu/simple/timing.cc | 1 | ||||
-rw-r--r-- | src/cpu/simple/timing.hh | 7 |
2 files changed, 5 insertions, 3 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 87a5245b2..075d05d81 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -109,7 +109,6 @@ TimingSimpleCPU::drain(DrainManager *drain_manager) if (_status == Idle || (_status == BaseSimpleCPU::Running && isDrained())) { - assert(!fetchEvent.scheduled()); DPRINTF(Drain, "No need to drain.\n"); return 0; } else { diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index cab2057ea..52807ba08 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -320,11 +320,14 @@ class TimingSimpleCPU : public BaseSimpleCPU * of a gem5 microcode sequence. * * <li>Stay at PC is true. + * + * <li>A fetch event is scheduled. Normally this would never be the + case with microPC() == 0, but right after a context is + activated it can happen. * </ul> */ bool isDrained() { - return microPC() == 0 && - !stayAtPC; + return microPC() == 0 && !stayAtPC && !fetchEvent.scheduled(); } /** |