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author | Ali Saidi <saidi@eecs.umich.edu> | 2007-09-28 13:21:30 -0400 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-09-28 13:21:30 -0400 |
commit | 887cd6a273f8777580fc3a046090c6b5244e9cad (patch) | |
tree | 8f053cad51065661938a4e12f7d82ebac4b4cfc8 /src/cpu/simple | |
parent | 58c448ced510835631527fa64a0ebd0b497b525b (diff) | |
download | gem5-887cd6a273f8777580fc3a046090c6b5244e9cad.tar.xz |
Update statistics to use cycles properly instead of ticks
--HG--
extra : convert_revision : 62911280b631ef24720f9ce701d1c19a9b8a9784
Diffstat (limited to 'src/cpu/simple')
-rw-r--r-- | src/cpu/simple/timing.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 8d1cf9a17..eee5b8cb5 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -180,7 +180,7 @@ TimingSimpleCPU::switchOut() { assert(status() == Running || status() == Idle); _status = SwitchedOut; - numCycles += curTick - previousTick; + numCycles += tickToCycles(curTick - previousTick); // If we've been scheduled to resume but are then told to switch out, // we'll need to cancel it. @@ -483,7 +483,7 @@ TimingSimpleCPU::fetch() advanceInst(fault); } - numCycles += curTick - previousTick; + numCycles += tickToCycles(curTick - previousTick); previousTick = curTick; } @@ -512,7 +512,7 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt) _status = Running; - numCycles += curTick - previousTick; + numCycles += tickToCycles(curTick - previousTick); previousTick = curTick; if (getState() == SimObject::Draining) { @@ -629,7 +629,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt) assert(_status == DcacheWaitResponse); _status = Running; - numCycles += curTick - previousTick; + numCycles += tickToCycles(curTick - previousTick); previousTick = curTick; Fault fault = curStaticInst->completeAcc(pkt, this, traceData); |