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author | Gabe Black <gblack@eecs.umich.edu> | 2007-03-07 20:04:45 +0000 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-03-07 20:04:45 +0000 |
commit | 8edc9d79cee3edd6d16a8254a0180aaa242974c7 (patch) | |
tree | 9ac7148f0862e81210fe929fcd61496ea7216727 /src/cpu/simple | |
parent | c82251326986affba0224460552236ebfe3447c2 (diff) | |
parent | 49527ab55312bf02dfce20c45db8f173b0c2324e (diff) | |
download | gem5-8edc9d79cee3edd6d16a8254a0180aaa242974c7.tar.xz |
Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem
--HG--
extra : convert_revision : d764fe37c71269a04fcede6cbf30e24262447e89
Diffstat (limited to 'src/cpu/simple')
-rw-r--r-- | src/cpu/simple/base.hh | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 01c8e8eb7..980ea2f96 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -284,14 +284,19 @@ class BaseSimpleCPU : public BaseCPU void setNextPC(uint64_t val) { thread->setNextPC(val); } void setNextNPC(uint64_t val) { thread->setNextNPC(val); } + MiscReg readMiscRegNoEffect(int misc_reg) + { + return thread->readMiscRegNoEffect(misc_reg); + } + MiscReg readMiscReg(int misc_reg) { return thread->readMiscReg(misc_reg); } - MiscReg readMiscRegWithEffect(int misc_reg) + void setMiscRegNoEffect(int misc_reg, const MiscReg &val) { - return thread->readMiscRegWithEffect(misc_reg); + return thread->setMiscRegNoEffect(misc_reg, val); } void setMiscReg(int misc_reg, const MiscReg &val) @@ -299,34 +304,29 @@ class BaseSimpleCPU : public BaseCPU return thread->setMiscReg(misc_reg, val); } - void setMiscRegWithEffect(int misc_reg, const MiscReg &val) - { - return thread->setMiscRegWithEffect(misc_reg, val); - } - MiscReg readMiscRegOperand(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; - return thread->readMiscReg(reg_idx); + return thread->readMiscRegNoEffect(reg_idx); } MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx) { int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; - return thread->readMiscRegWithEffect(reg_idx); + return thread->readMiscReg(reg_idx); } void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val) { int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; - return thread->setMiscReg(reg_idx, val); + return thread->setMiscRegNoEffect(reg_idx, val); } void setMiscRegOperandWithEffect( const StaticInst *si, int idx, const MiscReg &val) { int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; - return thread->setMiscRegWithEffect(reg_idx, val); + return thread->setMiscReg(reg_idx, val); } unsigned readStCondFailures() { |