summaryrefslogtreecommitdiff
path: root/src/cpu/simple
diff options
context:
space:
mode:
authorKevin Lim <ktlim@umich.edu>2006-07-07 16:47:28 -0400
committerKevin Lim <ktlim@umich.edu>2006-07-07 16:47:28 -0400
commitb2a479cfc89e3109830bd285b0819b6a0b56cbf4 (patch)
tree32ea9fd57f6c2bf90c31e62fab7a755f65f408b9 /src/cpu/simple
parent1faada9bd98a6425624a97813d4c8cdc5b78aa1f (diff)
parent7811500eefc57d8f9f00845b9187d9a1a6ef6655 (diff)
downloadgem5-b2a479cfc89e3109830bd285b0819b6a0b56cbf4.tar.xz
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge --HG-- extra : convert_revision : e8933f852352164f4e50444f94cc6ee260e06766
Diffstat (limited to 'src/cpu/simple')
-rw-r--r--src/cpu/simple/atomic.cc22
-rw-r--r--src/cpu/simple/atomic.hh2
-rw-r--r--src/cpu/simple/timing.cc26
-rw-r--r--src/cpu/simple/timing.hh2
4 files changed, 31 insertions, 21 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index b7202cbbb..12bfdeb9b 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -55,18 +55,28 @@ AtomicSimpleCPU::TickEvent::description()
return "AtomicSimpleCPU tick event";
}
+Port *
+AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
+{
+ if (if_name == "dcache_port")
+ return &dcachePort;
+ else if (if_name == "icache_port")
+ return &icachePort;
+ else
+ panic("No Such Port\n");
+}
void
AtomicSimpleCPU::init()
{
//Create Memory Ports (conect them up)
- Port *mem_dport = mem->getPort("");
- dcachePort.setPeer(mem_dport);
- mem_dport->setPeer(&dcachePort);
+// Port *mem_dport = mem->getPort("");
+// dcachePort.setPeer(mem_dport);
+// mem_dport->setPeer(&dcachePort);
- Port *mem_iport = mem->getPort("");
- icachePort.setPeer(mem_iport);
- mem_iport->setPeer(&icachePort);
+// Port *mem_iport = mem->getPort("");
+// icachePort.setPeer(mem_iport);
+// mem_iport->setPeer(&icachePort);
BaseCPU::init();
#if FULL_SYSTEM
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 951a8da06..179b4a721 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -122,6 +122,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
public:
+ virtual Port *getPort(const std::string &if_name, int idx = -1);
+
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index eb5895949..e55301c6b 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -37,19 +37,20 @@
using namespace std;
using namespace TheISA;
+Port *
+TimingSimpleCPU::getPort(const std::string &if_name, int idx)
+{
+ if (if_name == "dcache_port")
+ return &dcachePort;
+ else if (if_name == "icache_port")
+ return &icachePort;
+ else
+ panic("No Such Port\n");
+}
void
TimingSimpleCPU::init()
{
- //Create Memory Ports (conect them up)
- Port *mem_dport = mem->getPort("");
- dcachePort.setPeer(mem_dport);
- mem_dport->setPeer(&dcachePort);
-
- Port *mem_iport = mem->getPort("");
- icachePort.setPeer(mem_iport);
- mem_iport->setPeer(&icachePort);
-
BaseCPU::init();
#if FULL_SYSTEM
for (int i = 0; i < threadContexts.size(); ++i) {
@@ -463,12 +464,7 @@ TimingSimpleCPU::completeIfetch(Packet *pkt)
bool
TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
{
- if (cpu->_status == DcacheWaitResponse)
- cpu->completeDataAccess(pkt);
- else if (cpu->_status == IcacheWaitResponse)
- cpu->completeIfetch(pkt);
- else
- assert("OOPS" && 0);
+ cpu->completeIfetch(pkt);
return true;
}
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index f9bc0f352..0a3f91e6c 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -132,6 +132,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
public:
+ virtual Port *getPort(const std::string &if_name, int idx = -1);
+
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);