Merge zizzer:/bk/newmem

into  zeep.pool:/z/saidi/work/m5.newmem

src/cpu/simple/atomic.cc:
    merge steve's changes in.

--HG--
extra : convert_revision : a17eda37cd63c9380af6fe68b0aef4b1e1974231

4 files changed, 41 insertions, 4 deletions

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 6a536fbcd..072867536 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -31,6 +31,7 @@
 #include "arch/locked_mem.hh"
 #include "arch/mmaped_ipr.hh"
 #include "arch/utility.hh"
+#include "base/bigint.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/simple/atomic.hh"
 #include "mem/packet.hh"
@@ -151,6 +152,8 @@ AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
     data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
     data_write_pkt = new Packet(data_write_req, MemCmd::WriteReq,
                                 Packet::Broadcast);
+    data_swap_pkt = new Packet(data_write_req, MemCmd::SwapReq,
+                                Packet::Broadcast);
 }
 
 
@@ -318,6 +321,10 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
 
 template
 Fault
+AtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
+
+template
+Fault
 AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
 
 template
@@ -363,10 +370,15 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 {
     // use the CPU's statically allocated write request and packet objects
     Request *req = data_write_req;
-    PacketPtr pkt = data_write_pkt;
+    PacketPtr pkt;
 
     req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
 
+    if (req->isSwap())
+        pkt = data_swap_pkt;
+    else
+        pkt = data_write_pkt;
+
     if (traceData) {
         traceData->setAddr(addr);
     }
@@ -381,6 +393,11 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         if (req->isLocked()) {
             do_access = TheISA::handleLockedWrite(thread, req);
         }
+        if (req->isCondSwap()) {
+             assert(res);
+             req->setExtraData(*res);
+        }
+
 
         if (do_access) {
             pkt->reinitFromRequest();
@@ -401,7 +418,10 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 #endif
         }
 
-        if (res) {
+        if (req->isSwap()) {
+            assert(res);
+            *res = pkt->get<T>();
+        } else if (res) {
             *res = req->getScResult();
         }
     }
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 42c7bf23a..5bffb7666 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -118,6 +118,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU
     PacketPtr data_read_pkt;
     Request  *data_write_req;
     PacketPtr data_write_pkt;
+    PacketPtr data_swap_pkt;
 
     bool dcache_access;
     Tick dcache_latency;
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index a2b624139..01c8e8eb7 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -125,7 +125,7 @@ class BaseSimpleCPU : public BaseCPU
     MachInst inst;
 
     // Static data storage
-    TheISA::IntReg dataReg;
+    TheISA::LargestRead dataReg;
 
     StaticInstPtr curStaticInst;
     StaticInstPtr curMacroStaticInst;
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index e4748c966..ff3606a74 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -30,6 +30,7 @@
 
 #include "arch/locked_mem.hh"
 #include "arch/utility.hh"
+#include "base/bigint.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/simple/timing.hh"
 #include "mem/packet.hh"
@@ -312,6 +313,10 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
 
 template
 Fault
+TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
+
+template
+Fault
 TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
 
 template
@@ -359,13 +364,20 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
                     cpu_id, /* thread ID */ 0);
 
+    if (traceData) {
+        traceData->setAddr(req->getVaddr());
+    }
+
     // translate to physical address
     Fault fault = thread->translateDataWriteReq(req);
 
     // Now do the access.
     if (fault == NoFault) {
         assert(dcache_pkt == NULL);
-        dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
+        if (req->isSwap())
+            dcache_pkt = new Packet(req, MemCmd::SwapReq, Packet::Broadcast);
+        else
+            dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
         dcache_pkt->allocate();
         dcache_pkt->set(data);
 
@@ -374,6 +386,10 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         if (req->isLocked()) {
             do_access = TheISA::handleLockedWrite(thread, req);
         }
+        if (req->isCondSwap()) {
+             assert(res);
+             req->setExtraData(*res);
+        }
 
         if (do_access) {
             if (!dcachePort.sendTiming(dcache_pkt)) {