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| author | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2012-11-02 11:32:01 -0500 |
|---|---|---|
| committer | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2012-11-02 11:32:01 -0500 |
| commit | c0ab52799ca4ebd0a51363cfedd0658e6d79b842 (patch) | |
| tree | afdf65e4593c64bbc1d5b511aacbaf0fa4b558ad /src/cpu/simple | |
| parent | 044a6525876efc61838dffa89ac52425d510b754 (diff) | |
| download | gem5-c0ab52799ca4ebd0a51363cfedd0658e6d79b842.tar.xz | |
sim: Include object header files in SWIG interfaces
When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.
This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.
Diffstat (limited to 'src/cpu/simple')
| -rw-r--r-- | src/cpu/simple/AtomicSimpleCPU.py | 1 | ||||
| -rw-r--r-- | src/cpu/simple/BaseSimpleCPU.py | 1 | ||||
| -rw-r--r-- | src/cpu/simple/TimingSimpleCPU.py | 1 |
3 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py index 54daaec63..1927a5862 100644 --- a/src/cpu/simple/AtomicSimpleCPU.py +++ b/src/cpu/simple/AtomicSimpleCPU.py @@ -43,6 +43,7 @@ from BaseSimpleCPU import BaseSimpleCPU class AtomicSimpleCPU(BaseSimpleCPU): type = 'AtomicSimpleCPU' + cxx_header = "cpu/simple/atomic.hh" width = Param.Int(1, "CPU width") simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles") simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles") diff --git a/src/cpu/simple/BaseSimpleCPU.py b/src/cpu/simple/BaseSimpleCPU.py index d9b963890..a4ae7e34b 100644 --- a/src/cpu/simple/BaseSimpleCPU.py +++ b/src/cpu/simple/BaseSimpleCPU.py @@ -34,6 +34,7 @@ from DummyChecker import DummyChecker class BaseSimpleCPU(BaseCPU): type = 'BaseSimpleCPU' abstract = True + cxx_header = "cpu/simple/base.hh" def addCheckerCpu(self): if buildEnv['TARGET_ISA'] in ['arm']: diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py index 61491b087..72560366e 100644 --- a/src/cpu/simple/TimingSimpleCPU.py +++ b/src/cpu/simple/TimingSimpleCPU.py @@ -31,3 +31,4 @@ from BaseSimpleCPU import BaseSimpleCPU class TimingSimpleCPU(BaseSimpleCPU): type = 'TimingSimpleCPU' + cxx_header = "cpu/simple/timing.hh" |