tlb: More fixing of unified TLB

3 files changed, 44 insertions, 36 deletions

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index b5e65265a..601111588 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -314,7 +314,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
         req->setVirt(0, addr, dataSize, flags, thread->readPC());
 
         // translate to physical address
-        Fault fault = thread->dtb->translateAtomic(req, tc, false);
+        Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read);
 
         // Now do the access.
         if (fault == NoFault) {
@@ -452,7 +452,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         req->setVirt(0, addr, dataSize, flags, thread->readPC());
 
         // translate to physical address
-        Fault fault = thread->dtb->translateAtomic(req, tc, true);
+        Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write);
 
         // Now do the access.
         if (fault == NoFault) {
@@ -609,7 +609,8 @@ AtomicSimpleCPU::tick()
         bool fromRom = isRomMicroPC(thread->readMicroPC());
         if (!fromRom && !curMacroStaticInst) {
             setupFetchRequest(&ifetch_req);
-            fault = thread->itb->translateAtomic(&ifetch_req, tc, false, true);
+            fault = thread->itb->translateAtomic(&ifetch_req, tc,
+                                                 BaseTLB::Execute);
         }
 
         if (fault == NoFault) {
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 874eeefb7..1af2ea0ec 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -454,15 +454,15 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
 
         typedef SplitDataTranslation::WholeTranslationState WholeState;
         WholeState *state = new WholeState(req1, req2, req,
-                (uint8_t *)(new T), true);
+                                           (uint8_t *)(new T), BaseTLB::Read);
         thread->dtb->translateTiming(req1, tc,
-                new SplitDataTranslation(this, 0, state), false);
+                new SplitDataTranslation(this, 0, state), BaseTLB::Read);
         thread->dtb->translateTiming(req2, tc,
-                new SplitDataTranslation(this, 1, state), false);
+                new SplitDataTranslation(this, 1, state), BaseTLB::Read);
     } else {
-        thread->dtb->translateTiming(req, tc,
-                new DataTranslation(this, (uint8_t *)(new T), NULL, true),
-                false);
+        DataTranslation *translation =
+            new DataTranslation(this, (uint8_t *)(new T), NULL, BaseTLB::Read);
+        thread->dtb->translateTiming(req, tc, translation, BaseTLB::Read);
     }
 
     if (traceData) {
@@ -573,15 +573,15 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 
         typedef SplitDataTranslation::WholeTranslationState WholeState;
         WholeState *state = new WholeState(req1, req2, req,
-                (uint8_t *)dataP, false);
+                (uint8_t *)dataP, BaseTLB::Write);
         thread->dtb->translateTiming(req1, tc,
-                new SplitDataTranslation(this, 0, state), true);
+                new SplitDataTranslation(this, 0, state), BaseTLB::Write);
         thread->dtb->translateTiming(req2, tc,
-                new SplitDataTranslation(this, 1, state), true);
+                new SplitDataTranslation(this, 1, state), BaseTLB::Write);
     } else {
-        thread->dtb->translateTiming(req, tc,
-                new DataTranslation(this, (uint8_t *)dataP, res, false),
-                true);
+        DataTranslation *translation =
+            new DataTranslation(this, (uint8_t *)dataP, res, BaseTLB::Write);
+        thread->dtb->translateTiming(req, tc, translation, BaseTLB::Write);
     }
 
     if (traceData) {
@@ -671,8 +671,8 @@ TimingSimpleCPU::fetch()
         Request *ifetch_req = new Request();
         ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
         setupFetchRequest(ifetch_req);
-        thread->itb->translateTiming(ifetch_req, tc,
-                &fetchTranslation, false, true);
+        thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
+                BaseTLB::Execute);
     } else {
         _status = IcacheWaitResponse;
         completeIfetch(NULL);
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 731eeeefc..6f6b02bb7 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -102,11 +102,13 @@ class TimingSimpleCPU : public BaseSimpleCPU
         TimingSimpleCPU *cpu;
 
       public:
-        FetchTranslation(TimingSimpleCPU *_cpu) : cpu(_cpu)
+        FetchTranslation(TimingSimpleCPU *_cpu)
+            : cpu(_cpu)
         {}
 
-        void finish(Fault fault, RequestPtr req,
-                ThreadContext *tc, bool write, bool execute)
+        void
+        finish(Fault fault, RequestPtr req, ThreadContext *tc,
+               BaseTLB::Mode mode)
         {
             cpu->sendFetch(fault, req, tc);
         }
@@ -119,19 +121,22 @@ class TimingSimpleCPU : public BaseSimpleCPU
         TimingSimpleCPU *cpu;
         uint8_t *data;
         uint64_t *res;
-        bool read;
+        BaseTLB::Mode mode;
 
       public:
         DataTranslation(TimingSimpleCPU *_cpu,
-                uint8_t *_data, uint64_t *_res, bool _read) :
-            cpu(_cpu), data(_data), res(_res), read(_read)
-        {}
+                uint8_t *_data, uint64_t *_res, BaseTLB::Mode _mode)
+            : cpu(_cpu), data(_data), res(_res), mode(_mode)
+        {
+            assert(mode == BaseTLB::Read || mode == BaseTLB::Write);
+        }
 
         void
-        finish(Fault fault, RequestPtr req,
-                ThreadContext *tc, bool write, bool execute)
+        finish(Fault fault, RequestPtr req, ThreadContext *tc,
+               BaseTLB::Mode mode)
         {
-            cpu->sendData(fault, req, data, res, read);
+            assert(mode == this->mode);
+            cpu->sendData(fault, req, data, res, mode == BaseTLB::Read);
             delete this;
         }
     };
@@ -147,18 +152,20 @@ class TimingSimpleCPU : public BaseSimpleCPU
             RequestPtr mainReq;
             Fault faults[2];
             uint8_t *data;
-            bool read;
+            BaseTLB::Mode mode;
 
             WholeTranslationState(RequestPtr req1, RequestPtr req2,
-                    RequestPtr main, uint8_t *_data, bool _read)
+                    RequestPtr main, uint8_t *data, BaseTLB::Mode mode)
             {
+                assert(mode == BaseTLB::Read || mode == BaseTLB::Write);
+
                 outstanding = 2;
                 requests[0] = req1;
                 requests[1] = req2;
                 mainReq = main;
                 faults[0] = faults[1] = NoFault;
-                data = _data;
-                read = _read;
+                this->data = data;
+                this->mode = mode;
             }
         };
 
@@ -167,13 +174,13 @@ class TimingSimpleCPU : public BaseSimpleCPU
         WholeTranslationState *state;
 
         SplitDataTranslation(TimingSimpleCPU *_cpu, int _index,
-                WholeTranslationState *_state) :
-            cpu(_cpu), index(_index), state(_state)
+                WholeTranslationState *_state)
+            : cpu(_cpu), index(_index), state(_state)
         {}
 
         void
-        finish(Fault fault, RequestPtr req,
-                ThreadContext *tc, bool write, bool execute)
+        finish(Fault fault, RequestPtr req, ThreadContext *tc,
+               BaseTLB::Mode mode)
         {
             assert(state);
             assert(state->outstanding);
@@ -185,7 +192,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
                                    state->requests[1],
                                    state->mainReq,
                                    state->data,
-                                   state->read);
+                                   state->mode == BaseTLB::Read);
                 delete state;
             }
             delete this;