Clean up clock phase drift code a bit.

src/cpu/base.cc:
    Move clock phase drift code to the base CPU so that any CPU model can use it.
src/cpu/base.hh:
    Added two functions to help get the next cycle the CPU should be scheduled.
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
    Use the function now in BaseCPU.

--HG--
extra : convert_revision : 444494b66ffc85fc473c23f57683c5f9458ad80c

2 files changed, 11 insertions, 19 deletions

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 72249be41..4f68cfd6f 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -180,9 +180,7 @@ AtomicSimpleCPU::resume()
         changeState(SimObject::Running);
         if (thread->status() == ThreadContext::Active) {
             if (!tickEvent.scheduled()) {
-                Tick nextTick = curTick + cycles(1) - 1;
-                nextTick -= (nextTick % (cycles(1)));
-                tickEvent.schedule(nextTick);
+                tickEvent.schedule(nextCycle());
             }
         }
     }
@@ -211,9 +209,7 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
         ThreadContext *tc = threadContexts[i];
         if (tc->status() == ThreadContext::Active && _status != Running) {
             _status = Running;
-            Tick nextTick = curTick + cycles(1) - 1;
-            nextTick -= (nextTick % (cycles(1)));
-            tickEvent.schedule(nextTick);
+            tickEvent.schedule(nextCycle());
             break;
         }
     }
@@ -231,9 +227,7 @@ AtomicSimpleCPU::activateContext(int thread_num, int delay)
 
     notIdleFraction++;
     //Make sure ticks are still on multiples of cycles
-    Tick nextTick = curTick + cycles(delay + 1) - 1;
-    nextTick -= (nextTick % (cycles(1)));
-    tickEvent.schedule(nextTick);
+    tickEvent.schedule(nextCycle(curTick + cycles(delay)));
     _status = Running;
 }
 
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 4d57bf6d5..abf316095 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -532,14 +532,13 @@ TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
 {
     if (pkt->isResponse()) {
         // delay processing of returned data until next CPU clock edge
-        Tick time = pkt->req->getTime();
-        while (time < curTick)
-            time += lat;
+        Tick mem_time = pkt->req->getTime();
+        Tick next_tick = cpu->nextCycle(mem_time);
 
-        if (time == curTick)
+        if (next_tick == curTick)
             cpu->completeIfetch(pkt);
         else
-            tickEvent.schedule(pkt, time);
+            tickEvent.schedule(pkt, next_tick);
 
         return true;
     }
@@ -610,14 +609,13 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
 {
     if (pkt->isResponse()) {
         // delay processing of returned data until next CPU clock edge
-        Tick time = pkt->req->getTime();
-        while (time < curTick)
-            time += lat;
+        Tick mem_time = pkt->req->getTime();
+        Tick next_tick = cpu->nextCycle(mem_time);
 
-        if (time == curTick)
+        if (next_tick == curTick)
             cpu->completeDataAccess(pkt);
         else
-            tickEvent.schedule(pkt, time);
+            tickEvent.schedule(pkt, next_tick);
 
         return true;
     }