MEM: Introduce the master/slave port sub-classes in C++

This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.

The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.

The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.

The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.

2 files changed, 9 insertions, 8 deletions

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index e5b3bd67d..d7ad07a5e 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -65,14 +65,14 @@ AtomicSimpleCPU::TickEvent::description() const
     return "AtomicSimpleCPU tick";
 }
 
-Port *
-AtomicSimpleCPU::getPort(const string &if_name, int idx)
+MasterPort &
+AtomicSimpleCPU::getMasterPort(const string &if_name, int idx)
 {
     if (if_name == "physmem_port") {
         hasPhysMemPort = true;
-        return &physmemPort;
+        return physmemPort;
     } else {
-        return BaseCPU::getPort(if_name, idx);
+        return BaseCPU::getMasterPort(if_name, idx);
     }
 }
 
@@ -94,7 +94,7 @@ AtomicSimpleCPU::init()
     }
 
     if (hasPhysMemPort) {
-        AddrRangeList pmAddrList = physmemPort.getPeer()->getAddrRanges();
+        AddrRangeList pmAddrList = physmemPort.getSlavePort().getAddrRanges();
         physMemAddr = *pmAddrList.begin();
     }
     // Atomic doesn't do MT right now, so contextId == threadId
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 8a1c9000f..126cd3765 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -112,10 +112,11 @@ class AtomicSimpleCPU : public BaseSimpleCPU
   public:
 
     /**
-     * Override the getPort of the BaseCPU so that we can provide a pointer
-     * to the physmemPort, unique to the Atomic CPU.
+     * Override the getMasterPort of the BaseCPU so that we can
+     * provide the physmemPort, unique to the Atomic CPU.
      */
-    virtual Port *getPort(const std::string &if_name, int idx = -1);
+    virtual MasterPort &getMasterPort(const std::string &if_name,
+                                      int idx = -1);
 
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);