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| author | Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> | 2017-04-05 13:24:23 -0500 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
| commit | 166da650a3c864b31193ade893ed99e547c67644 (patch) | |
| tree | 84236bf28007885e864e885fab8e715e332affa6 /src/cpu/simple | |
| parent | 00da08902918da13fccc3f2266b7b2f5d0080708 (diff) | |
| download | gem5-166da650a3c864b31193ade893ed99e547c67644.tar.xz | |
arch: ISA parser additions of vector registers
Reiley's update :) of the isa parser definitions. My addition of the
vector element operand concept for the ISA parser. Nathanael's modification
creating a hierarchy between vector registers and its constituencies to the
isa parser.
Some fixes/updates on top to consider instructions as vectors instead of
floating when they use the VectorRF. Some counters added to all the
models to keep faithful counts.
Change-Id: Id8f162a525240dfd7ba884c5a4d9fa69f4050101
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2706
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/cpu/simple')
| -rw-r--r-- | src/cpu/simple/base.cc | 16 | ||||
| -rw-r--r-- | src/cpu/simple/exec_context.hh | 6 |
2 files changed, 22 insertions, 0 deletions
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 57cea4ba7..783967602 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -252,6 +252,11 @@ BaseSimpleCPU::regStats() .desc("Number of float alu accesses") ; + t_info.numVecAluAccesses + .name(thread_str + ".num_vec_alu_accesses") + .desc("Number of vector alu accesses") + ; + t_info.numCallsReturns .name(thread_str + ".num_func_calls") .desc("number of times a function call or return occured") @@ -272,6 +277,11 @@ BaseSimpleCPU::regStats() .desc("number of float instructions") ; + t_info.numVecInsts + .name(thread_str + ".num_vec_insts") + .desc("number of vector instructions") + ; + t_info.numIntRegReads .name(thread_str + ".num_int_register_reads") .desc("number of times the integer registers were read") @@ -613,6 +623,12 @@ BaseSimpleCPU::postExecute() t_info.numFpInsts++; } + //vector alu accesses + if (curStaticInst->isVector()){ + t_info.numVecAluAccesses++; + t_info.numVecInsts++; + } + //number of function calls/returns to get window accesses if (curStaticInst->isCall() || curStaticInst->isReturn()){ t_info.numCallsReturns++; diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh index 0f546407d..6d51e5ed9 100644 --- a/src/cpu/simple/exec_context.hh +++ b/src/cpu/simple/exec_context.hh @@ -94,6 +94,9 @@ class SimpleExecContext : public ExecContext { // Number of float alu accesses Stats::Scalar numFpAluAccesses; + // Number of vector alu accesses + Stats::Scalar numVecAluAccesses; + // Number of function calls/returns Stats::Scalar numCallsReturns; @@ -106,6 +109,9 @@ class SimpleExecContext : public ExecContext { // Number of float instructions Stats::Scalar numFpInsts; + // Number of vector instructions + Stats::Scalar numVecInsts; + // Number of integer register file accesses Stats::Scalar numIntRegReads; Stats::Scalar numIntRegWrites; |