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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-03 13:10:26 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-11 16:55:30 +0000 |
| commit | 2113b21996d086dab32b9fd388efe3df241bfbd2 (patch) | |
| tree | 26d944027f726dde3ec49b67538663ccc41bcad3 /src/cpu/simple | |
| parent | 59505f7305cc3f3b7637233fd2d231bd7f561e80 (diff) | |
| download | gem5-2113b21996d086dab32b9fd388efe3df241bfbd2.tar.xz | |
misc: Substitute pointer to Request with aliased RequestPtr
Every usage of Request* in the code has been replaced with the
RequestPtr alias. This is a preparing patch for when RequestPtr will be
the typdefed to a smart pointer to Request rather then a raw pointer to
Request.
Change-Id: I73cbaf2d96ea9313a590cdc731a25662950cd51a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10995
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Diffstat (limited to 'src/cpu/simple')
| -rw-r--r-- | src/cpu/simple/atomic.cc | 4 | ||||
| -rw-r--r-- | src/cpu/simple/base.cc | 2 | ||||
| -rw-r--r-- | src/cpu/simple/base.hh | 2 | ||||
| -rw-r--r-- | src/cpu/simple/timing.cc | 2 |
4 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 7a368ab32..0e7c59f6a 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -331,7 +331,7 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size, SimpleThread* thread = t_info.thread; // use the CPU's statically allocated read request and packet objects - Request *req = &data_read_req; + RequestPtr req = &data_read_req; if (traceData) traceData->setMem(addr, size, flags); @@ -435,7 +435,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr, } // use the CPU's statically allocated write request and packet objects - Request *req = &data_write_req; + RequestPtr req = &data_write_req; if (traceData) traceData->setMem(addr, size, flags); diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 36a2cb06c..025c7a3ea 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -468,7 +468,7 @@ BaseSimpleCPU::checkForInterrupts() void -BaseSimpleCPU::setupFetchRequest(Request *req) +BaseSimpleCPU::setupFetchRequest(RequestPtr req) { SimpleExecContext &t_info = *threadInfo[curThread]; SimpleThread* thread = t_info.thread; diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 15ab2aba4..64fa58d92 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -129,7 +129,7 @@ class BaseSimpleCPU : public BaseCPU void checkForInterrupts(); - void setupFetchRequest(Request *req); + void setupFetchRequest(RequestPtr req); void preExecute(); void postExecute(); void advancePC(const Fault &fault); diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 083de2b40..657c2976f 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -620,7 +620,7 @@ TimingSimpleCPU::fetch() if (needToFetch) { _status = BaseSimpleCPU::Running; - Request *ifetch_req = new Request(); + RequestPtr ifetch_req = new Request(); ifetch_req->taskId(taskId()); ifetch_req->setContext(thread->contextId()); setupFetchRequest(ifetch_req); |