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authorAli Saidi <saidi@eecs.umich.edu>2007-03-02 22:34:51 -0500
committerAli Saidi <saidi@eecs.umich.edu>2007-03-02 22:34:51 -0500
commit4e8d2d1593475008b926829e6944a59963166079 (patch)
tree42ff01c4146f48c23179de7d2b01f4e6bdbe97d7 /src/cpu/simple
parentd8ada247f4fb107e7dc530ceb96a624d46c8ed9a (diff)
downloadgem5-4e8d2d1593475008b926829e6944a59963166079.tar.xz
make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way as the twin 64 bit loads
src/arch/isa_parser.py: src/arch/sparc/isa/decoder.isa: src/arch/sparc/isa/operands.isa: src/base/bigint.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/mem/packet_access.hh: make ldtw(a) Twin 32 bit load work correctly --HG-- extra : convert_revision : 2646b269d58cc1774e896065875a56cf5e313b42
Diffstat (limited to 'src/cpu/simple')
-rw-r--r--src/cpu/simple/atomic.cc4
-rw-r--r--src/cpu/simple/timing.cc4
2 files changed, 8 insertions, 0 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 3001241fe..df7e780e6 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -321,6 +321,10 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
template
Fault
+AtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
+
+template
+Fault
AtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
template
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index ff3606a74..7f857c68d 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -317,6 +317,10 @@ TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
template
Fault
+TimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
+
+template
+Fault
TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
template