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author | Stephen Hines <hines@cs.fsu.edu> | 2008-02-06 16:32:40 -0500 |
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committer | Stephen Hines <hines@cs.fsu.edu> | 2008-02-06 16:32:40 -0500 |
commit | 6cc1573923754ecb406d03ab4d807f928737c294 (patch) | |
tree | 08e407623fedf71b04b128eb93734d4f51988b36 /src/cpu/simple | |
parent | 0ccf9a2c3751f160d7d51153ef468a60b4daf8d0 (diff) | |
download | gem5-6cc1573923754ecb406d03ab4d807f928737c294.tar.xz |
Make the Event::description() a const function
--HG--
extra : convert_revision : c7768d54d3f78685e93920069f5485083ca989c0
Diffstat (limited to 'src/cpu/simple')
-rw-r--r-- | src/cpu/simple/atomic.cc | 2 | ||||
-rw-r--r-- | src/cpu/simple/atomic.hh | 2 | ||||
-rw-r--r-- | src/cpu/simple/timing.cc | 2 | ||||
-rw-r--r-- | src/cpu/simple/timing.hh | 8 |
4 files changed, 7 insertions, 7 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index aa548b46f..2254d44d5 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -55,7 +55,7 @@ AtomicSimpleCPU::TickEvent::process() } const char * -AtomicSimpleCPU::TickEvent::description() +AtomicSimpleCPU::TickEvent::description() const { return "AtomicSimpleCPU tick"; } diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index f14dd6f99..19bc0e13b 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -68,7 +68,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU TickEvent(AtomicSimpleCPU *c); void process(); - const char *description(); + const char *description() const; }; TickEvent tickEvent; diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index e1fc6882f..9fe3d2fff 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -822,7 +822,7 @@ TimingSimpleCPU::IprEvent::process() } const char * -TimingSimpleCPU::IprEvent::description() +TimingSimpleCPU::IprEvent::description() const { return "Timing Simple CPU Delay IPR event"; } diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index 79fbe0f5f..f8b77604a 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -101,7 +101,7 @@ class TimingSimpleCPU : public BaseSimpleCPU TickEvent(TimingSimpleCPU *_cpu) :Event(&mainEventQueue), cpu(_cpu) {} - const char *description() { return "Timing CPU tick"; } + const char *description() const { return "Timing CPU tick"; } void schedule(PacketPtr _pkt, Tick t); }; @@ -127,7 +127,7 @@ class TimingSimpleCPU : public BaseSimpleCPU ITickEvent(TimingSimpleCPU *_cpu) : TickEvent(_cpu) {} void process(); - const char *description() { return "Timing CPU icache tick"; } + const char *description() const { return "Timing CPU icache tick"; } }; ITickEvent tickEvent; @@ -155,7 +155,7 @@ class TimingSimpleCPU : public BaseSimpleCPU DTickEvent(TimingSimpleCPU *_cpu) : TickEvent(_cpu) {} void process(); - const char *description() { return "Timing CPU dcache tick"; } + const char *description() const { return "Timing CPU dcache tick"; } }; DTickEvent tickEvent; @@ -219,7 +219,7 @@ class TimingSimpleCPU : public BaseSimpleCPU TimingSimpleCPU *cpu; IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t); virtual void process(); - virtual const char *description(); + virtual const char *description() const; }; void completeDrain(); |